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参数资料
| 型号： | PC16552DV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, CC-44 |
| 文件页数： | 15/21页 |
| 文件大小： | 291K |
| 代理商： | PC16552DV |
8.0 Registers
(Continued)
Two identical register sets, one for each channel, are in the
DUART. All register descriptions in this section apply to the
register sets in both channels.
8.1 LINE CONTROL REGISTER
The system programmer specifies the format of the asyn-
chronous data communications exchange and sets the Divi-
sor Latch Access bit via the Line Control Register (LCR).
This is a read and write register. Table II shows the contents
of the LCR. Details on each bit follow:
Bits 0 and 1:
These two bits specify the number of data bits
in each transmitted or received serial character. The encod-
ing of bits 0 and 1 is as follows:
Bit 1
Bit 0
Data Length
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2:
This bit specifies the number of Stop bits transmitted
with each serial character. If bit 2 is a logic 0, one Stop bit is
generated in the transmitted data. If bit 2 is a logic 1 when a
5-bit data length is selected, one and a half Stop bits are
generated. If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit
word length is selected, two Stop bits are generated. The
receiver checks the first Stop bit only, regardless of the
number of Stop bits selected.
Bit 3:
This bit is the Parity Enable bit. When bit 3 is a logic 1,
a Parity bit is generated (transmit data) or checked (receive
data) between the last data bit and Stop bit of the serial
data. (The Parity bit is used to produce an even or odd
number of 1s when the data bits and the Parity bit are
summed.)
Bit 4:
This bit is the Even Parity Select bit. When parity is
enabled and bit 4 is a logic 0, an odd number of logic 1s is
transmitted or checked in the data word bits and Parity bit.
When parity is enabled and bit 4 is a logic 1, an even num-
ber of logic 1s is transmitted or checked.
Bit 5:
This bit is the Stick Parity bit. When parity is enabled it
is used in conjunction with bit 4 to select Mark or Space
Parity. When bits 3, 4 and 5 are logic 1 the Parity bit is
transmitted and checked as a logic 0 (Space Parity). If bits 3
and 5 are 1 and bit 4 is a logic 0 then the Parity bit is
transmitted and checked as a logic 1 (Mark Parity). If bit 5 is
a logic 0 Stick Parity is disabled.
Bit 6:
This bit is the Break Control bit. It causes a break
condition to be transmitted to the receiving UART. When it
is set to a logic 1, the serial output (SOUT) is forced to the
Spacing state (logic 0). The break is disabled by setting bit 6
to a logic 0. The Break Control bit acts only on SOUT and
has no effect on the transmitter logic.
Composite Serial Data
TL/C/9426–21
Note:
This feature enables the CPU to alert a terminal in a computer com-
munications system. If the following sequence is followed, no errone-
ous or extraneous characters will be transmitted because of the
break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (TEMT
e
1), and clear break when
normal transmission has to be restored.
During the break, the Transmitter can be used as a character timer to accu-
rately establish the break duration.
Bit 7:
This bit is the Divisor Latch Access Bit (DLAB). It must
be set high (logic 1) to access the Divisor Latches of the
Baud Generator or the Alternate Function Register during a
Read or Write operation. It must be set low (logic 0) to ac-
cess any other register.
8.2 TYPICAL CLOCK CIRCUITS
TL/C/9426–18
TL/C/9426–19
Typical Crystal Oscillator Network (Note)
Crystal
R
P
1 M
X
R
X2
1.5k
C
1
C
2
3.1 MHz
10–30 pF
40–60 pF
1.8 MHz
1 M
X
1.5k
10–30 pF
40–60 pF
Note:
These R and C values are approximate and may vary 2 x depending
on the crystal characteristics. All crystal circuits should be designed
specifically for the system.
15
相关PDF资料 |
PDF描述 |
|---|---|
| PC16553 | WRISTLOCK TERMINAL |
| PC16553V | Dual Universal Asynchronous Receiver/Transmitter with FIFOs plus High Performance Parallel Interface |
| PC21100 | KPTC 8C 8#16 PIN PLUG |
| PC33094DW | IGNITION CONTROL |
| PC33253DW | Full Bridge Pre-Driver |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC16552DV NS024AV (AND AJ) | 制造商:Texas Instruments 功能描述: |
| PC16552DV | 制造商:Texas Instruments 功能描述:DUAL UART FIFO SMD 16552 PLCC44 |
| PC16552DV/NOPB | 功能描述:UART 接口集成电路 DUAL UNIV ASYNCHRON RCVR/TRANS W/ FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552DVX | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552DVX(PBF) | 制造商:National Semiconductor Corporation 功能描述: |
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