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| 型号： | PC33888PNBR2 |
| 厂商： | Motorola, Inc. |
| 英文描述： | Quad High-Side and Octal Low-Side Switch for Automotive |
| 中文描述： | 四高边和八路低端汽车开关 |
| 文件页数： | 16/32页 |
| 文件大小： | 667K |
| 代理商： | PC33888PNBR2 |
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33888
16
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 6.0 V
≤
V
PWR
≤
27 V, 4.5 V
≤
V
DD
≤
5.5 V, -40
°
C
≤
T
J
≤
150
°
C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
High-Side Output Rising Fast Slew Rate
(Note 27)
6.0 V < V
PWR
< 9.0 V
9.0 V < V
PWR
< 16 V
16 V < V
PWR
< 27 V
SR
R_FAST
0.03
0.05
0.1
–
0.5
–
0.6
0.8
1.1
V/
μ
s
High-Side Output Rising Slow Slew Rate
(Note 28)
6.0 V < V
PWR
< 9.0 V
9.0 V < V
PWR
< 16 V
16 V < V
PWR
< 27 V
SR
R_SLOW
0.01
0.01
0.01
–
0.08
–
0.14
0.18
0.2
V/
μ
s
High-Side Output Falling Fast Slew Rate
(Note 27)
6.0 V < V
PWR
< 9.0 V
9.0 V < V
PWR
< 16 V
16 V < V
PWR
< 27 V
SR
F_FAST
0.2
0.3
0.5
–
0.8
–
1.0
1.5
2.2
V/
μ
s
High-Side Output Falling Slow Slew Rate
(Note 28)
6.0 V < V
PWR
< 9.0 V
9.0 V < V
PWR
< 16 V
16 V < V
PWR
< 27 V
SR
F_SLOW
0.05
0.08
0.08
–
0.15
–
0.3
0.4
0.5
V/
μ
s
High-Side Output Turn ON Delay Time
(Note 29)
t
DLY(ON)
5.0
30
150
μ
s
High-Side Output Turn OFF Delay Time
(Note 30)
t
DLY(OFF)
5.0
80
150
μ
s
Low-Side Output Falling Slew Rate
(Note 31)
SR
F
0.5
3.0
10
V/
μ
s
Low-Side Output Rising Slew Rate
(Note 31)
SR
R
1.0
6.0
20
V/
μ
s
Low-Side Output Turn ON Delay Time
(Note 32)
t
DLY(ON)
0.5
2.0
10
μ
s
Low-Side Output Turn OFF Delay Time
(Note 33)
t
DLY(OFF)
0.5
4.0
10
μ
s
Low-Side Output Fault Delay Timer
(Note 34)
t
DLY(
FS
)
70
150
250
μ
s
Watchdog Timeout
(Note 35)
t
WDTO
340
584
770
ms
Notes
27.
High-side output rise and fall fast slew rates measured across a 5.0
resistive load at high-side output = 0.5 V to V
PWR
-3.0 V (see
Figure 2
,
page 18). These parameters are guaranteed by process monitoring.
High-side output rise and fall slow slew rates measured across a 5.0
resistive load at high-side output = 0.5 V to V
PWR
-3.0 V (see
Figure 2
, page 18). These parameters are guaranteed by process monitoring.
High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with R
L
= 27
resistive load (see
Figure 2
,
page 18).
High-side output turn-OFF delay time measured from 50% of the falling IHS to V
PWR
-2.0 V of the output OFF with R
L
= 27
resistive load
(see
Figure 2
, page 18).
Low-side output rise and fall slew rates measured across a 5.0
resistive load at low-side output = 10% to 90% (see
Figure 3
, page 18).
Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of V
OUT
with R
L
= 27
resistive load (see
Figure 3
,
page 18).
Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of V
OUT
with R
L
= 27
resistive load (see
Figure 3
,
page 18). These parameters are guaranteed by process monitoring.
Propagation time of Short Fault Disable Report Delay measured from rising edge of
CS
to output disabled, low-side = 5.0 V, and device
configured for low-side output overcurrent latchoff using CLOCCR.
Watchdog timeout delay is measured from the rising edge of WAKE or
RST
from the sleep state to the HS[0:1] turn-ON with the outputs
driven OFF and the FSI floating. The accuracy of
t
WDTO
is maintained for all configured watchdog timeouts.
28.
29.
30.
31.
32.
33.
34.
35.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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