参数资料
| 型号： | PCA85132U/2DB/Q1,0 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 44/62页 |
| 文件大小： | 0K |
| 描述： | IC LCD DRIVER 32 UNCASED |
| 标准包装： | 600 |
| 显示器类型： | LCD |
| 配置： | 多重 |
| 接口： | I²C |
| 数字或字符： | 任何数字类型 |
| 电流 - 电源： | 60µA |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 模具 |
| 供应商设备封装： | 模具 |
| 包装： | 散装 |
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NXP Semiconductors
PCA85132
LCD driver for low multiplex rates
14.3 SDA and SDAACK configuration
The Serial DAta line (SDA) and the I 2 C-bus acknowledge line (SDAACK) are split. Both
lines can be connected together to facilitate a single-line SDA.
SDA
SDAACK
two wire mode
SDA
SDAACK
single wire mode
013aaa111
Fig 33. SDA, SDAACK configurations
14.4 Cascaded operation
In large display configurations, up to 8 PCA85132 can be distinguished on the same
I 2 C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable
I 2 C-bus slave address (SA0).
Table 23.
Addressing cascaded PCA85132
Cluster
1
2
Bit SA0
0
1
Pin A1
0
0
1
1
0
0
1
1
Pin A0
0
1
0
1
0
1
0
1
Device
0
1
2
3
4
5
6
7
When cascaded PCA85132 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCA85132 of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see Figure 34
For display sizes that are not multiple of 640 elements, a mixed cascaded system can be
considered containing only devices like PCA85132 and PCA85133. Depending on the
application, one must take care of the software commands compatibility and pin
connection compatibility.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85132. This synchronization is guaranteed after the Power-On Reset (POR). The
only time that SYNC is likely to be needed is if synchronization is accidentally lost (for
example, by noise in adverse electrical environments, or by the definition of a multiplex
mode when PCA85132 with different SA0 levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an open-drain driver with an
internal pull-up resistor. A PCA85132 asserts the SYNC line at the onset of its last active
backplane signal and monitors the SYNC line at all other times. Should synchronization in
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCA85133 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DA/Q1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DA/Q1,0 | 功能描述:IC LCD DRIVER UNIV UNCASED RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
| PCA85133U/2DB/Q1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DB/Q1,0 | 功能描述:IC LCD DRIVER UNIV UNCASED RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
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