参数资料
型号: PCA8576CH/Q900/1,1
厂商: NXP Semiconductors
文件页数: 18/54页
文件大小: 0K
描述: IC LCD DRIVER 40SEG I2C 64LQFP
产品培训模块: I²C Bus Fundamentals
标准包装: 1
显示器类型: LCD
配置: 40 段
接口: I²C
电流 - 电源: 120µA
电源电压: 2 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 标准包装
其它名称: 568-5122-6
NXP Semiconductors
PCA8576C
Automotive LCD driver for low multiplex rates
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
? In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
? In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
? In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
? In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAM is a static 40 ? 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
? the bits in the RAM bitmap and the LCD elements
? the RAM columns and the segment outputs
? the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map Figure 12 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 12. Display RAM bit map
When display data is transmitted to the PCA8576C, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
PCA8576C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 December 2013
? NXP B.V. 2013. All rights reserved.
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