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参数资料
| 型号： | PCA9502BS,128 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 19/25页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 24HVQFN |
| 标准包装： | 1,500 |
| 接口： | I²C，SPI |
| 输入/输出数： | 8 |
| 中断输出： | 无 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-HVQFN（4x4） |
| 包装： | 带卷 (TR) |
| 其它名称： | 935281363128 PCA9502BS-F PCA9502BS-F-ND |
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
3 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
6.
Pinning information
6.1 Pinning
6.2 Pin description
a. I2C-bus interface
b. SPI interface
Fig 3.
Pin conguration for HVQFN24
GPIO7
GPIO6
GPIO5
GPIO4
VSS
GPIO2
GPIO1
GPIO0
SCL
n.c.
A1
A0
VDD
RESET
VDD
GPIO3
V
DD
V
SS
SDA
002aab839
Transparent top view
V
DD
V
SS
V
DD
terminal 1
index area
6
13
5
14
4
15
3
16
2
17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
PCA9502BS
IRQ
GPIO7
GPIO6
GPIO5
GPIO4
VSS
GPIO2
GPIO1
GPIO0
SCLK
SO
SI
CS
VSS
VDD
RESET
VDD
GPIO3
V
DD
V
SS
V
SS
002aab840
Transparent top view
V
DD
V
SS
V
DD
terminal 1
index area
6
13
5
14
4
15
3
16
2
17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
PCA9502BS
IRQ
Table 2.
Pin description
Symbol
Pin
Type
Description
RESET
1
I
device hardware reset (active LOW)[1]
VDD
2, 3, 11,
22, 24
-
power supply
I2C/SPI
4
I
I2C-bus or SPI interface select. I2C-bus interface is selected if this
pin is at logic HIGH. SPI interface is selected if this pin is at logic
LOW.
CS/A0
5
I
SPI chip select or I2C-bus device address select A0. If SPI
conguration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt trigger, active LOW). If I2C-bus conguration
is selected by I2C/SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SI/A1
6
I
SPI data input pin or I2C-bus device address select A1. If SPI
conguration is selected by I2C/SPI pin, this is the SPI data input
pin. If I2C-bus conguration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to Table 11.
SO
7
O
SPI data output pin. If SPI conguration is selected by I2C/SPI
pin, this is a 3-stateable output pin. If I2C-bus conguration is
selected by I2C/SPI pin, this pin function is undened and must
be left as n.c. (not connected).
SCL/SCLK
8
I
I2C-bus or SPI input clock.
SDA
9
I/O
I2C-bus data input/output, open-drain if I2C-bus conguration is
selected by I2C/SPI pin. If SPI conguration is selected then this
pin is an undened pin and must be connected to VSS.
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