参数资料
型号: PCA9507DP,118
厂商: NXP Semiconductors
文件页数: 19/20页
文件大小: 0K
描述: IC I/O EXPANDER I2C 24B 8TSSOP
产品培训模块: I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 1
接口: I²C,SM 总线
输入/输出数: 2 输入,2 输出
中断输出:
频率 - 时钟: 400kHz
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-TSSOP
包装: 标准包装
其它名称: 568-5924-6
PCA9507_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 7 February 2008
8 of 20
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I2C-bus and SMBus
According to Figure 6, when port A of the PCA9507 is pulled LOW by a driver on the
I2C-bus, a comparator detects the falling edge when it goes below 0.3VCC(A) and causes
the internal driver on port B to turn on, causing port B to pull down to about 0.5 V. When
port B of the PCA9507 falls, rst a CMOS hysteresis type input detects the falling edge
and causes the internal driver on port A to turn on and pull the port A pin down to ground.
In order to illustrate what would be seen in a typical application, refer to Figure 11 and
If the bus master in Figure 6 were to write to the slave through the PCA9507, waveforms
shown in Figure 11 would be observed on the A bus. This looks like a normal I2C-bus
transmission except that the HIGH level may be as low as 2.7 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
The master drives the B bus to ground or lets it oat to VCC(B) as it sends data to the slave
at the falling edge of the 8th clock, master releases SDAB on the B bus and slave pulls
SDAA on the A bus to ground, causing the PCA9507 to pull SDAB on the B bus to 0.5 V.
At the falling edge of the 9th clock, the master again drives the B bus and slave releases
the A bus.
Multiple PCA9507 port A sides can be connected in a star conguration (Figure 9),
allowing all nodes to communicate with each other.
Multiple PCA9507s can be connected in series (Figure 10) as long as port A is connected
to port B. I2C-bus slave devices can be connected to any of the bus segments. The
number of devices that can be connected in series is limited by repeater
delay/time-of-ight considerations on the maximum bus speed requirements.
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