参数资料
型号: PCA9633DP2,118
厂商: NXP Semiconductors
文件页数: 29/43页
文件大小: 0K
描述: IC LED DRIVER RGBA 10-TSSOP
产品培训模块: LED Controllers
I²C Bus Fundamentals
标准包装: 1
拓扑: 开路漏极,PWM
输出数: 4
内部驱动器: 两者兼有
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGBA
频率: 25MHz
电源电压: 2.3 V ~ 5.5 V
输出电压: 5.5V
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-TSSOP
包装: 标准包装
工作温度: -40°C ~ 85°C
产品目录页面: 845 (CN2011-ZH PDF)
配用: OM6276,598-ND - DEMO BOARD PWM LED
622-1004-ND - BOARD DEMO FOR PHILIPS PCA9633
其它名称: 568-3237-6
NXP Semiconductors
PCA9633
4-bit Fm+ I 2 C-bus LED driver
Table 20. Static characteristics …continued
V DD = 2.3 V to 5.5 V; V SS = 0 V; T amb = ? 40 ° C to +85 ° C; unless otherwise speci?ed.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Address inputs
V IL
LOW-level input voltage
? 0.5
-
+0.3V DD V
V IH
I LI
C i
HIGH-level input voltage
input leakage current
input capacitance
0.7V DD
? 1
-
-
-
3.7
5.5
+1
5
V
μ A
pF
[1]
[2]
V DD must be lowered to 0.2 V in order to reset part.
Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.
13. Dynamic characteristics
Table 21.
Dynamic characteristics
Symbol Parameter
Conditions
Standard- mode
Fast-mode
Fast-mode
Unit
I 2 C-bus
I 2 C-bus
Plus I 2 C-bus
Min
Max
Min
Max
Min
Max
f SCL
t BUF
SCL clock frequency
bus free time between a
[1]
0
4.7
100
-
0
1.3
400
-
0
0.5
1000
-
kHz
μ s
STOP and START condition
t HD;STA
hold time (repeated) START
4.0
-
0.6
-
0.26
-
μ s
condition
t SU;STA
set-up time for a repeated
4.7
-
0.6
-
0.26
-
μ s
START condition
t SU;STO
set-up time for STOP
4.0
-
0.6
-
0.26
-
μ s
condition
t HD;DAT
data hold time
0
-
0
-
0
-
ns
t VD;ACK
t VD;DAT
t SU;DAT
t LOW
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL
[2]
[3]
0.3
0.3
250
4.7
3.45
3.45
-
-
0.1
0.1
100
1.3
0.9
0.9
-
-
0.05
0.05
50
0.5
0.45
0.45
-
-
μ s
μ s
ns
μ s
clock
t HIGH
HIGH period of the SCL
4.0
-
0.6
-
0.26
-
μ s
clock
t f
fall time of both SDA and
[5][6]
-
300
20 + 0.1C b [4]
300
-
120
ns
SCL signals
t r
rise time of both SDA and
-
1000
20 + 0.1C b [4]
300
-
120
ns
SCL signals
t SP
pulse width of spikes that
[7]
-
50
-
50
-
50
ns
must be suppressed by the
input ?lter
[1]
[2]
[3]
[4]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
C b = total capacitance of one bus line in pF.
PCA9633_5
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 25 July 2008
29 of 43
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