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参数资料
| 型号： | PCF85103C-2T/00:11 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 100KHZ 8SOIC |
| 产品培训模块： | I²C Bus Fundamentals |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 6.0 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 管件 |
| 其它名称： | 568-5748 935262039112 PCF85103C-2T/00:11-ND PCF85103C2D PCF85103C2D-ND |
Philips Semiconductors
PCF85103C-2
256 × 8-bit CMOS EEPROM with I 2 C-bus interface
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3
Device addressing
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF85103C-2 is shown in Figure 4 . To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either V DD or V SS .
0
0
1
0
A2
A1
A0 R/W
FIXED
HARDWARE
SELECTABLE
002aaa253
Fig 4. Slave address.
The last bit of the slave address de?nes the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
9397 750 14218
8.1.4
Write operations
Byte/word write: For a write operation, the PCF85103C-2 requires a second
address ?eld. This address ?eld is a word address providing access to the 256 words
of memory. Upon receipt of the word address, the PCF85103C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I 2 C-bus.
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 22 October 2004
7 of 20
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| PCF85116-3 | 制造商:NXP Semiconductors 功能描述: |
| PCF85116-3D | 功能描述:电可擦除可编程只读存储器 2048X8 电可擦除可编程只读存储器 I2C 2.7V EXT RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| PCF85116-3N | 功能描述:电可擦除可编程只读存储器 2048 X 8 电可擦除可编程只读存储器 ISC 2.7V EXT RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| PCF85116-3P | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2048 x 8-bit CMOS EEPROM with I2C-bus interface |
| PCF85116-3P/01 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2048 x 8-bit CMOS EEPROM with I2C-bus interface |
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