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参数资料
| 型号： | PCF85132U/2DA/1,02 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 28/62页 |
| 文件大小： | 0K |
| 描述： | IC LCD DISPLAY DRVR UNCASED |
| 标准包装： | 600 |
| 显示器类型： | LCD |
| 配置： | 多重 |
| 接口： | I²C |
| 数字或字符： | 任何数字类型 |
| 电流 - 电源： | 60µA |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 模具 |
| 供应商设备封装： | 模具 |
| 包装： | 散装 |
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NXP Semiconductors
PCF85132
LCD driver for low multiplex rates
8. Characteristics of the I 2 C-bus
The I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF85132, the SDA line becomes fully
I 2 C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence, it may be possible that the acknowledge generated by the PCF85132
cannot be interpreted as logic 0 by the master. In COG applications where the
acknowledge cycle is required, it is therefore necessary to minimize the track resistance
from the SDAACK pin to the system SDA line to guarantee a valid LOW level (see
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I 2 C-bus master has to be set up in such a way that it ignores the
acknowledge cycle. 2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 17 ).
SDA
SCL
data line
stable;
change
of data
data valid
allowed
mba607
Fig 17. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
2.
PCF85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 July 2013
? NXP B.V. 2013. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCF85133 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF85133U/2DA/1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF85133U/2DA/1,02 | 功能描述:IC LCD DRIVER UNIV UNCASED DIE RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
| PCF85133U/2DA/1,026 | 制造商:NXP Semiconductors 功能描述: |
| PCF85134 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
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