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参数资料
型号： PCF8536AT/1,118
厂商： NXP Semiconductors
文件页数： 60/74页
文件大小： 0K
描述： IC LCD DRIVER LOW MPLEX 56TSSOP
特色产品： NXP - I2C Interface
标准包装： 1
显示器类型： LED，LCD
配置： 7段 + DP，14段 + DP + AP，点阵
接口： I²C
数字或字符： 20 字符，40 字符，320 元件
电源电压： 1.8 V ~ 5.5 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 56-TFSOP（0.240"，6.10mm 宽）
供应商设备封装： 56-TSSOP
包装： 标准包装
其它名称： 568-8447-6
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
t RESET(L)
RESET
0.3V DD
013aaa475
Fig 48. RESET timing
Table 45. Timing characteristics: I 2 C-bus
V DD = 1.8 V to 5.5 V; V SS = 0 V; V LCD = 2.5 V to 9.0 V; T amb = ? 40 ? C to +85 ? C; unless otherwise specified. All timing values
are valid within the operating supply voltage and temperature range and referenced to V IL and V IH with an input voltage swing
of V SS to V DD . Timing waveforms see Figure 49 .
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pin SCL
f SCL
t LOW
t HIGH
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
[1]
-
1.3
0.6
-
-
-
400
-
-
kHz
? s
? s
Pin SDA
t SU;DAT
t HD;DAT
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
Pins SCL and SDA
t BUF
bus free time between a STOP
1.3
-
-
? s
and START condition
t SU;STO
t HD;STA
set-up time for STOP condition
hold time (repeated) START
0.6
0.6
-
-
-
-
? s
? s
condition
t SU;STA
set-up time for a repeated START
0.6
-
-
? s
condition
t r
t f
rise time of both SDA and SCL
signals
fall time of both SDA and SCL
f SCL = 400 kHz
f SCL = 100 kHz
-
-
-
-
-
-
0.3
1.0
0.3
? s
? s
? s
signals
t VD;ACK
t VD;DAT
C b
t SP
data valid acknowledge time
data valid time
capacitive load for each bus line
pulse width of spikes that must be
[2]
[3]
[4]
0.6
0.6
-
-
-
-
-
-
-
-
400
50
? s
? s
pF
ns
suppressed by the input filter
[1]
[2]
[3]
[4]
The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL
is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
t VD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
t VD;DAT = minimum time for valid SDA output following SCL LOW.
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF8536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 February 2012
? NXP B.V. 2012. All rights reserved.
60 of 74
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