参数资料
| 型号： | PCF8578H/1,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 16/46页 |
| 文件大小： | 0K |
| 描述： | IC LCD DRVR ROW/CLMN 64-LQFP |
| 标准包装： | 1,500 |
| 显示器类型： | LCD |
| 配置： | 点阵 |
| 接口： | I²C |
| 电源电压： | 2.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 935276284118 PCF8578H/1-T PCF8578H/1-T-ND |
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NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
8.5 Oscillator
8.5.1 Internal clock
The clock signal for the system may be generated by the internal oscillator and prescaler.
The frequency is determined by the value of the resistor R ext(OSC) , see Figure 10 . For
normal use a value of 330 k ? is recommended. The clock signal, for cascaded
PCF8579s, is output at CLK and has a frequency of 1 ? 6 (multiplex rate 1:8, 1:16 and 1:32)
or 1 ? 8 (multiplex rate 1:24) of the oscillator frequency.
10 3
f osc
(kHz)
10 2
10
1
msa837
10
10 2
10 3
10 4
R ext(OSC) (k ? )
To avoid capacitive coupling, which could adversely affect oscillator stability, R ext(OSC) should be
placed as closely as possible to the OSC pin. If this proves to be a problem, a ?ltering capacitor
may be connected in parallel to R ext(OSC) .
Fig 10. Oscillator frequency as a function of external oscillator resistor, R ext(OSC)
8.5.2 External clock
If an external clock is used, OSC must be connected to V DD and the external clock signal
to CLK. Table 8 summarizes the nominal CLK and SYNC frequencies.
Table 8.
Signal frequencies required for nominal 64 Hz frame frequency [1]
Oscillator frequency,
Frame frequency,
Multiplex rate, Division ratio Clock frequency,
f osc (Hz) [2]
12288
f fr (Hz)
64
(1:n)
1:8, 1:16, 1:32 6
f clk (Hz)
2048
12288
64
1:24
8
1536
[1]
[2]
A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
R ext(OSC) = 330 k ? .
8.6 Timing generator
The timing generator of the PCF8578 organizes the internal data ?ow of the device and
generates the LCD frame synchronization pulse SYNC, whose period is an integer
multiple of the clock period. In cascaded applications, this signal maintains the correct
timing relationship between the PCF8578 and PCF8579s in the system.
PCF8578_6
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
16 of 46
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