参数资料
型号: PCF8578H/1,118
厂商: NXP Semiconductors
文件页数: 18/46页
文件大小: 0K
描述: IC LCD DRVR ROW/CLMN 64-LQFP
标准包装: 1,500
显示器类型: LCD
配置: 点阵
接口: I²C
电源电压: 2.5 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
其它名称: 935276284118
PCF8578H/1-T
PCF8578H/1-T-ND
NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
8.8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal the end of a data transmission to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
SDA
SCL
data line
stable;
change
of data
Fig 11. Bit transfer
SDA
SCL
S
START condition
data valid
allowed
mba607
P
STOP condition
mba608
Fig 12. De?nition of START and STOP condition
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mba605
Fig 13. System con?guration
PCF8578_6
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
18 of 46
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