参数资料
型号: PCM3168APAPR
厂商: Texas Instruments
文件页数: 13/68页
文件大小: 0K
描述: IC 24-BIT AUDIO CODEC 64-HTQFP
标准包装: 1,000
类型: 音频编解码器
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 6 / 8
三角积分调变:
S/N 比,标准 ADC / DAC (db): 107 / 112(差分),104 / 112(单端)
动态范围,标准 ADC / DAC (db): 107 / 112(差分),104 / 112(单端)
电压 - 电源,模拟: 4.5 V ~ 5.5 V
电压 - 电源,数字: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-TQFP 裸露焊盘
供应商设备封装: 64-HTQFP(10x10)
包装: 带卷 (TR)
其它名称: 296-31710-2
PCM3168APAPR-ND
VOLTAGE REFERENCES
SYSTEM CLOCK INPUT
SystemClock
(SCKI)
High
Low
t
SCL
t
SCH
t
SCY
2.0V
0.8V
SAMPLING MODE
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
The PCM3168A and PCM3168A-Q1 include two internal references for the six-channel ADCs; these references
correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog
ground via decoupling capacitors. In addition, the PCM3168A and PCM3168A-Q1 include two pins for
common-mode voltage output (VCOMDA for DACs and VCOMAD for ADCs). These pins should be also
connected with an analog ground via decoupling capacitors. Furthermore, both common pins can be used to bias
external high-impedance circuits, if they are required.
The PCM3168A and PCM3168A-Q1 require an external system clock input applied at the SCKI input for ADC
and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The
multiples supported in ADC operation include 256 fS, 384 fS, 512 fS, and 768 fS; the multiples supported in DAC
operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS. Details for these system clock multiples are
shown in Table 3. Figure 30 and Table 4 show the SCKI timing requirements.
Table 3. System Clock Frequencies for Common Audio Sampling Rates
SAMPLING
DEFAULT
FREQUENCY
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING
MODE
fS (kHz)
128 fS
(1)
192 fS
(1)
256 fS
384 fS
512 fS
768 fS
8
N/A
2.0480
3.0720(2)
4.0960
6.1440
16
2.0480(1)
3.0720(1)
4.0960
6.1440(2)
8.1920
12.2880
Single rate
32
4.0960(1)
6.1440(1)
8.1920
12.2880(2)
16.3840
24.5760
44.1
5.6488(1)
8.4672(1)
11.2896
16.9344(2)
22.5792
33.8688
48
6.1440(1)
9.2160(1)
12.2880
18.4320(2)
24.5760
36.8640
88.2
11.2896(3)
16.9344(3)
22.5792
33.8688
N/A
Dual rate
96
12.2880(3)
18.4320(3)
24.5760
36.8640
N/A
176.4(3)
22.5792(3)
33.8688(3)
N/A
Quad rate(3)
192(3)
24.5760(3)
36.8640(3)
N/A
(1)
Supported only by DAC operation
(2)
Requires 50% duty cycle for stable ADC performance.
(3)
Supported only by DAC operation
Figure 30. System Clock Timing Requirements
Table 4. Timing Requirements for Figure 30
SYMBOL
PARAMETER
MIN
MAX
UNIT
tSCY
System clock pulse cycle time
27
ns
tSCH
System clock pulse width high
10
ns
tSCL
System clock pulse width low
10
ns
tDTY
System clock pulse duty cycle
40
60
%
The PCM3168A and PCM3168A-Q1 support two sampling modes (single rate and dual rate) in ADC operation,
and three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC
and DAC operate at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is
supported for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an
20
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
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