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参数资料
| 型号： | PCM3794RHBTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 43/67页 |
| 文件大小： | 1417K |
| 代理商： | PCM3794RHBTG4 |
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SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007
MBST: BCK Output Configuration in Master Mode
Default value: 0
This bit is used to control the BCK output configuration in master mode. In master mode, this bit sets the BCK
output configuration to normal mode or burst mode. In normal mode (MBST = 0), the BCK clock runs
continuously. In burst mode (MBST = 1), the BCK clock runs intermittently, and the number of clock cycles per
LRCK period is reduced to equal the number of bits of audio data being transmitted. Operating in burst mode
reduces the power consumption of VIO (I/O cell power supply). This is effective in master mode (register 69
MSTR = 1).
MBST = 0
Normal output (default)
MBST = 1
Burst output
ATOD: ADC Digital Output to DAC Digital Input (Loopback)
Default value: 0
The ADC digital output is internally connected to the DAC digital input by setting ATOD = 1. This setting can be
used to debug ADC functions or to monitor a recording.
ATOD= 0
Disabled (default)
ATOD= 1
Enabled
ZCRS: Zero-Cross for Digital Attenuation/Mute and Analog Gain Setting
Default value: 0
This bit is used to enablethe zero-cross detector, which reduces zipper noise while the digital soft mute, digital
attenuation analog gain setting, or analog volume setting is being changed. If no zero-cross data is input for a
512/fS period (10.6 ms at a 48-kHz sampling rate), then a time-out occurs and the PCM3793/94 starts changing
the attenuation, gain, or volume level. The zero-cross detector cannot be used with continuous-zero and dc
data.
ZCRS = 0
Zero cross disabled (default)
ZCRS = 1
Zero cross enabled
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