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参数资料
| 型号： | PE33361MLIAA |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QCC48 |
| 封装： | 7 X 7 MM, GREEN, QFN-48 |
| 文件页数： | 10/15页 |
| 文件大小： | 344K |
| 代理商： | PE33361MLIAA |
Advance Information
PE33361
Page 4 of 15
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0287-01
│ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions (continued)
Note 1:
VDD pins 5, 6, 17, 18, 28, 30 and 48 are connected by diodes and must be supplied with the same positive voltage level.
VDD pins 26 and 35 are used to enable test modes and should be left floating.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
Pin No.
Pin Name
Interface Mode
Type
Description
26
VDD-fp
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
27
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
28
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
29
Cext
ALL
Output
Logical “NAND” of PD_UB and PD_DB terminated through an on chip, 2 k
series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
30
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
32
PD_DB
ALL
Output
PD_DB is pulse down when fp leads fc.
33
PD_UB
ALL
PD_UB is pulse down when fc leads fp.
35
VDD-fc
ALL
(Note 1)
VDD for fc. Can be left floating or connected to GND to disable the fc output.
36
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
38
GND
ALL
Ground.
39
GND
ALL
Ground.
40
fr
ALL
Input
Reference frequency input.
41
LD
ALL
Output,
OD
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD
is high impedance, otherwise LD is a logic low (“0”).
42
EnhB
Serial, Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
25
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
GND
ALL
Ground.
34
N/C
ALL
No Connect
37
GND
ALL
Ground.
43
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
44
R0
Direct
Input
R Counter bit0 (LSB).
45
R1
Direct
Input
R Counter bit1.
46
R2
Direct
Input
R Counter bit2.
47
R3
Direct
Input
R Counter bit3.
48
GND
ALL
(Note 1)
Ground.
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