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参数资料
| 型号： | PE3339-12 |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PDSO20 |
| 封装： | MO-153AC, TSSOP-20 |
| 文件页数： | 11/12页 |
| 文件大小： | 143K |
| 代理商： | PE3339-12 |
PE3339
Advance Information
Copyright
Peregrine Semiconductor Corp. 2004
File No. 70/0048~02A
|
UTSi CMOS RFIC SOLUTIONS
Page 8 of 12
Table 7. Primary Register Programming
Interface Mode
Enh
R5
R4
M8
M7
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Reserved
fp Output
Power
down
Counter
load
MSEL
output
fc output
Reserved
Serial*
0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Figure 4. Serial Interface Mode Timing Diagram
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
Sdata
Sclk
S_WR
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