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参数资料
| 型号： | PE3339-12 |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PDSO20 |
| 封装： | MO-153AC, TSSOP-20 |
| 文件页数： | 12/12页 |
| 文件大小： | 143K |
| 代理商： | PE3339-12 |
PE3339
Advance Information
PEREGRINE SEMICONDUCTOR CORP. | http://www.psemi.com
Copyright
Peregrine Semiconductor Corp. 2004
Page 9 of 12
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
fp output
Drives the M counter output onto the Dout output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
fc output
Drives the reference counter output onto the Dout output
Bit 7
Reserved**
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (fc leads fp),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, fp and fc.
The signals from the phase detector couple directly
to a charge pump. PD_U controls a current source
at pin CP with constant amplitude and pulse
duration approximately the same as PD_U. PD_D
similarly drives a current sink at pin CP. The
current pulses from pin CP are low pass filtered
externally and then connected to the VCO tune
voltage. PD_U pulses result in a current source,
which increases the VCO frequency and PD_D
results in a current sink, which decreases VCO
frequency when using a positive Kv VCO.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Figure 5. Typical PE3339 Loop Filter Application Example
R
C1
C2
Charge
Pum p
To VCO
Tune
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