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参数资料
| 型号： | PE64904MLBB-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC RF DTC 100MHZ-3GHZ 10QFN |
| 标准包装： | 3,000 |
| 系列： | UltraCMOS™ |
| 功能： | 数字调谐式电容器 |
| 频率： | 100MHz ~ 3GHz |
| RF 型： | 通用 |
| 封装/外壳： | 10-XFQFN |
| 包装： | 带卷 (TR) |
| 其它名称： | 1046-1054-2 CG PE64904 PE64904MLAA-Z PE64904MLAA-Z-ND PE64904MLAB-Z |
PE64904
Product Specification
Serial Interface Operation and Sharing
The PE64904 is controlled by a three wire SPI-
compatible interface. As shown in Figure 16 , the serial
master initiates the start of a telegram by driving the
SEN (Serial Enable) line high. Each bit of the 8-bit
telegram is clocked in on the rising edge of the SCL
(Serial Clock) line. SDA bits are clocked by most
significant bit (MSB) first, as shown in Table 5 and
Figure 16 . Transactions on SDA (Serial Data) are
allowed on the falling edge of SCL. The DTC activates
the data on the falling edge of SEN. The DTC does not
count how many bits are clocked and only maintains
the last 8 bits it received.
More than 1 DTC can be controlled by one interface by
utilizing a dedicated enable (SEN) line for each DTC.
SDA, SCL, and V DD lines may be shared as shown in
Figure 17 . Dedicated SEN lines act as a chip select such
that each DTC will only respond to serial transactions
intended for them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common SEN
can be used. This allows all DTCs to change states
simultaneously, but requires all DTCs to be programmed
even if the state is not changed.
Figure 16. Serial Interface Timing Diagram (oscilloscope view)
t EPW
t ESU
t DSU t DHD
t R
t F
1/f CLK
t EHD
SEN
SCL
SDA
b0
b7
b6
b5
b4
b3
b2
b1
b0
DTC Data
D m-2 <7:0>
D m-1 <7:0>
D m <7:0>
Table 5. Register Map
Figure 17. Recommended Bus sharing
b7
0
b6
0
b5
STB
1
b4
d4
b3
d3
b2
d2
b1
d1
b0
d0
V DD
V DD
DTC 1
RF+
MSB
(first in)
Note 1: The DTC is active when low (set to 0) and in
low-current stand-by mode when high (set to 1)
LSB
(last in)
SDA
SCL
SDA
SCL
SEN1
SEN
Table 6. Serial Interface Timing Characteristics
V DD = 2.6V, -40°C < T A < +85°C, unless otherwise specified
SEN2
DGND
RF-
GND
Symbol
Parameter
Min
Max
Units
f CLK
t R
t F
t ESU
t EHD
Serial Clock Frequency
SCL, SDA, SEN Rise Time
SCL, SDA, SEN Fall Time
SEN rising edge to SCL rising
edge
SCL rising edge to SEN falling
edge
19.2
19.2
26
6.5
6.5
MHz
ns
ns
ns
ns
V DD
SDA
SCL
SEN
DTC 2
RF+
t DSU
t DHD
t EOW
SDA valid to SCL rising edge
SDA valid after SCL rising edge
SEN falling edge to SEN rising
edge
13.2
13.2
38.4
ns
ns
ns
DGND
RF-
GND
Document No. 70-0325-06 │ www.psemi.com
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PE64905 | 制造商:PEREGRINE 制造商全称:PEREGRINE 功能描述:UltraCMOS?? Digitally Tunable Capacitor (DTC) 100 - 3000 MHz |
| PE64905MLAB-Z | 功能描述:IC RF DTC 100MHZ-3GHZ 10QFN RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:UltraCMOS™ 标准包装:100 系列:* |
| PE64905MLBB-Z | 制造商:Peregrine Semiconductor 功能描述:RF DTC 100MHZ-3GHZ 10QFN 制造商:Peregrine Semiconductor 功能描述:DIGITALLY TUNABLE CAPACITOR IC |
| PE64906 | 制造商:PSEMI 制造商全称:PSEMI 功能描述:UltraCMOS?? Digitally Tunable Capacitor (DTC) 100 - 3000 MHz |
| PE64906MLAA-Z | 制造商:Peregrine Semiconductor 功能描述:DIGITALLY TUNABLE CAPACITOR IC |
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