- 您现在的位置：买卖IC网 > PDF目录18822 > PE64904MLBB-Z (Peregrine Semiconductor)IC RF DTC 100MHZ-3GHZ 10QFN PDF资料下载
参数资料
| 型号： | PE64904MLBB-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC RF DTC 100MHZ-3GHZ 10QFN |
| 标准包装： | 3,000 |
| 系列： | UltraCMOS™ |
| 功能： | 数字调谐式电容器 |
| 频率： | 100MHz ~ 3GHz |
| RF 型： | 通用 |
| 封装/外壳： | 10-XFQFN |
| 包装： | 带卷 (TR) |
| 其它名称： | 1046-1054-2 CG PE64904 PE64904MLAA-Z PE64904MLAA-Z-ND PE64904MLAB-Z |
PE64904
Product Specification
Layout Recommendations
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF-pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
Figure 19. Recommended Schematic of
Multiple DTCs
Evaluation Board
The 101-0597 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Series (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B ( ε r = 3.48) and 2 inner
layers of FR4 ( ε r = 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using
a trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
Figure 21. Evaluation Board Layout
Figure 20. Recommended Layout of Multiple DTCs
101-0597
Document No. 70-0325-06 │ www.psemi.com
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
相关PDF资料 |
PDF描述 |
|---|---|
| MCD220-08IO1 | MOD THYRISTOR/DIODE 800V Y2-DCB |
| T7S0176504DN | SCR PHASE CTRL MOD 1700V 650A |
| MG-B-8-0 | CORD PATCH MINI CLIP 8" BLACK |
| T820029004DH | SCR PHASE CTRL MOD 200V 900A |
| VVZ175-16IO7 | RECT BRIDGE 3PH 167A 1600V PWSE2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PE64905 | 制造商:PEREGRINE 制造商全称:PEREGRINE 功能描述:UltraCMOS?? Digitally Tunable Capacitor (DTC) 100 - 3000 MHz |
| PE64905MLAB-Z | 功能描述:IC RF DTC 100MHZ-3GHZ 10QFN RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:UltraCMOS™ 标准包装:100 系列:* |
| PE64905MLBB-Z | 制造商:Peregrine Semiconductor 功能描述:RF DTC 100MHZ-3GHZ 10QFN 制造商:Peregrine Semiconductor 功能描述:DIGITALLY TUNABLE CAPACITOR IC |
| PE64906 | 制造商:PSEMI 制造商全称:PSEMI 功能描述:UltraCMOS?? Digitally Tunable Capacitor (DTC) 100 - 3000 MHz |
| PE64906MLAA-Z | 制造商:Peregrine Semiconductor 功能描述:DIGITALLY TUNABLE CAPACITOR IC |
发布紧急采购，3分钟左右您将得到回复。