- 您现在的位置：买卖IC网 > PDF目录378049 > PEB20324 (INFINEON TECHNOLOGIES AG) ICs for Communications PDF资料下载
参数资料
| 型号： | PEB20324 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成电路 |
| 文件页数： | 22/63页 |
| 文件大小： | 705K |
| 代理商： | PEB20324 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
PEB 20324
PEF 20324
Pin Descriptions
Hardware Reference Manual
22
04.99
19
FRAME
s/t/s
Frame
FRAME indicates the beginning and end of an access.
FRAME is asserted to indicate a bus transaction is
beginning. While FRAME is asserted, data transfers
continue. When FRAME is deasserted, the
transaction is in the final phase.
When MUNICH128X is Master, FRAME is an output.
When MUNICH128X is Slave, FRAME is an input.
FRAME is sampled on the rising edge of CLK.
Initiator Ready
IRDY indicates the bus master’s ability to complete the
current data phase of the transaction. It is used in
conjunction with TRDY. A data phase is completed on
any clock where both IRDY and TRDY are sampled
asserted. During a write, IRDY indicates that valid
data is present on AD(31:0). During a read, it indicates
the master is prepared to accept data. Wait cycles are
inserted until both IRDY and TRDY are asserted
together.
When MUNICH128X is Master, IRDY is an output.
When MUNICH128X is Slave, IRDY is an input.
IRDY is sampled on the rising edge of CLK.
Target Ready
TRDY indicates a slave’s ability to complete the
current data phase of the transaction. During a read,
TRDY indicates that valid data is present on AD(31:0).
During a write, it indicates the target is prepared to
accept data.
When MUNICH128X is Master, TRDY is an input.
When MUNICH128X is Slave, TRDY is an output.
TRDY is sampled on the rising edge of CLK.
STOP
STOP is used by a slave to request the current master
to stop the current bus transaction.
When MUNICH128X is Master, STOP is an input.
When MUNICH128X is Slave, STOP is an output.
STOP is sampled on the rising edge of CLK.
20
IRDY
s/t/s
21
TRDY
s/t/s
23
STOP
s/t/s
Table 2-5
Pin No.
Pin Descriptions by Functional Block: PCI Interface
(cont’d)
Symbol
Type Description
相关PDF资料 |
PDF描述 |
|---|---|
| PEF20532 | 2 Channel Serial Optimized Communication Controller |
| PEB20532 | 2 Channel Serial Optimized Communication Controller |
| PEF20534 | DMA Supported Serial Communication Controller with 4 Channels |
| PEB20534 | DMA Supported Serial Communication Controller with 4 Channels |
| PEB20534H-10 | DMA Supported Serial Communication Controller with 4 Channels DSCC4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PEB20324HV-2.1 | 制造商:Siemens 功能描述: |
| PEB20324HV2.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEB20324HV2.2-M128X | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEB20324HV22M128X | 制造商:Infineon Technologies AG 功能描述: |
| PEB2032HV3.2 | 制造商:Siemens 功能描述: |
发布紧急采购，3分钟左右您将得到回复。