Rev. A 11/09/10
4
PFS704-729EG
www.powerint.com
Figure 3.
Functional Block Diagram.
Pin Functional Description
VOLTAGE MONITOR (V) Pin:
The V pin is tied to the rectified AC rail through an external
resistor. Internal circuitry detects the peak of the input line
voltage which resembles a full-wave rectified waveform. The
rectified high-voltage bus is connected directly to the V pin
voltage through a large resistor (4 M
W for PFS70x and PFS71x;
9 M
W for PFS72x) to minimize power dissipation and standby
power consumption. A small ceramic capacitor (0.1
mF for
PFS70x and PFS71x; 0.047
mF for PFS72x) is required from the
VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass
any switching noise present on the rectified bus. This pin also
features both brown-in and brown-out protection.
FEEDBACK (FB) Pin:
The FEEDBACK pin is high input-impedance reference terminal
that connects to a feedback resistor network. This pin will also
feature fast overvoltage and undervoltage detection circuitry
that will disengage the internal power MOSFET in the event of a
system fault. A 10 nF capacitor is required between the
FEEDBACK to SIGNAL GROUND pins; this capacitor must be
placed very close to the device on the PCB to bypass any
switching noise. This pin is also used for loop compensation.
BIAS POWER (VCC) Pin:
This is a 10-12 VDC bias supply used to power the IC. The bias
voltage must be externally clamped to prevent the VCC pin
from exceeding 13.4 VDC.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the G pin.
The
SIGNAL GROUND pin must not be tied to the SOURCE pin.
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the tab and drain connection of the internal power switch.
Figure 2.
Pin Configuration.
PI-5333-113010
+
-
+
-
+
-
+
-
“Off-time derived with
constant Volt-Sec
Input Voltage
Emulation
VOFF is a function of the error-voltage (VE) and is used to reduce the average
operating frequency as a function of output power for increased efficiency
(PFS704-716).
(VOFF = 0.8 V for PFS723-729).
The internal derived error-voltage (VE)
regulates the output voltage
MON is the switch current
sense scale factor which
is function of peak line
voltage derived from IVIN
Fast OV
Comparator
FB
OV/UV
OTP
VCC
VOLTAGE MONITOR (V)
SIGNAL GROUND (G)
SOURCE (S)
BIAS POWER (VCC)
DRAIN (D)
FEEDBACK (FB)
FB
UV/
FB
OFF
VCC+
MON
Internal
Reference
V
REF
Transconductance
Error-Amplifier
Driver
I
OCP
Sense
FET
Power
MOSFET
UV Comparator
TIMER
SUPERVISOR
INPUT
LINE INTERFACE
Peak
Detector
INTERNAL
SUPPLY
OTP
SOFT
START
+
-
+
-
+
-
+
-
6 V
CINT
MON IS
CINT
VO-VIN
IVPK
Input UV
(IUV-/IUV+)
IS
LEB
OCP
1 kHz
Filter
7 kHz
Filter
Comparator
VOFF
V
OFF
VE
V
E
Frequency
Slide
Comparator
Latch
Input UV
FB
OV
PI-5334-083110
Exposed Pad
(Backside)
Internally
Connected to
DRAIN Pin
(see eSIP-7G
Package
Drawing)
Exposed Metal
(On Edge)
Internally
Connected to
DRAIN Pin
Exposed Metal (On Edge)
Internally Connected
to GROUND Pin
E Package (eSIP-7G)
1 2 3 4 5
7
V FB VCC G S
D
7
5 4 3 2 1
D
S G VCC FB V