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| 型号： | PGA308AIDGSTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 8/29页 |
| 文件大小： | 962K |
| 代理商： | PGA308AIDGSTG4 |
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SBOS440B – JULY 2008 – REVISED DECEMBER 2010
www.ti.com
under-scale
limit
level.
If
over-scale/under-scale
DIGITAL INTERFACE: ONE-WIRE PROGRAM
limiting is disabled, the PGA308 output voltage is
PROTOCOL
driven within 100mV (IOUT < 4mA) of either VS or
The PGA308 can be configured through a single-wire,
ground, depending on the selected fault polarity (high
UART-compatible interface (1W pin). It is possible to
or low).
connect this single-wire communication pin to the
VOUT pin in true three-terminal modules (VS, ground,
Additional Fault Detection
and sensor out) and continue to allow for calibration
There are five additional fault detect comparators
and configuration programming.
(internal fault comparators) that help detect subtle
All
communication
transactions
start
with
an
PGA308 front-end violations that could result in linear
initialization byte transmitted by the controller. This
voltages at VOUT and be interpreted as valid states.
byte
(55h)
sets
the
baud
rate
used
for
the
These comparators are especially useful during
communication transaction. The baud rate is sensed
factory calibration and setup.
during the initialization byte of every transaction, and
is used throughout the entire transaction. Each
Alarm Register
transaction may use a different baud rate, if desired.
Each of nine fault conditions sets a corresponding bit
Baud rates of 4.8k to 114k bits/second are supported.
in the Alarm register. The state of the fault condition
Each communication consists of several bytes of
can be read digitally from the Alarm register.
data. Each byte consists of 10-bit periods. The first bit
is the start bit and is always '0'. When idle, the 1W
OVER-SCALE AND UNDER-SCALE LIMITS
pin should always be high. The second through ninth
bits are the eight data bits for the byte and are
The
over-scale
and
under-scale
limit
circuitry
transferred LSB first. The 10th bit is the stop bit and
provides a programmable upper and lower clip limit
is always '1'.
for the PGA308 output voltage. When combined with
the fault monitor circuitry, system diagnostics can be
The second byte is a command/address byte. The
performed to determine if a conditioned sensor is
last bit in this byte indicates either a read or write at
defective, or if the process being monitored by the
the address selected by the address pointer portion
sensor is out of range. The selected PGA308 VLIM is
of the byte. Additional data transfer occurs after the
divided down by a precision resistor string to form the
command/address byte. The number of bytes and
over- and under-scale trip points. These resistor
direction of data transfer depend on the command
ratios are extremely accurate and produce no
byte. For a read sequence, the PGA308 waits for a
significant initial or temperature errors. An over-scale
2-bit delay (unless programmed otherwise) after the
amplifier driven by the over-scale threshold limits
completion of the command/address byte before
(clips) the maximum PGA308 output, VOUT. Similarly,
beginning to transmit. This wait allows time for the
an under-scale amplifier driven by the under-scale
controller to ensure that the PGA308 is able to control
threshold limits (clips) the minimum PGA308 output,
the One-Wire interface. The first byte transmitted by
VOUT. The reference for the trip points, VLIM, is
the PGA308 is the least significant byte of the register
register-selectable for either VREF or VS.
and the second byte will be the most significant byte
of the register.
DOUT/VCLAMP PIN
The recommended circuit implementation is to use a
The dual-use DOUT/VCLAMP pin functions either as a
pull-up resistor and/or current source with an open
VOUT clamp or as a digital push-pull output. The
drain (or open collector) output connected to the 1W
voltage clamp function provides an output voltage
pin, which is also an open drain output. The single
clamp, which is external-resistor programmable. In
wire can be driven high by the controller during
mixed-voltage systems, where the PGA308 may run
transmit from the controller, but some form of pull-up
from +5V with its output scaled for 0.1V to 2.9V,
is required to allow the signal to go high during
VCLAMP can be set to 3.0V to prevent an over-voltage
receive because the PGA308 1W pin can only pull
lock-up/latch-up condition on a 3V system ADC or
the output low.
microcontroller input. When programmed as a digital
output this pin can be used for sensor module
configuration. The value may be pre-programmed in
the
one-time
programmable
(OTP)
banks,
or
controlled through the One-Wire interface (1W pin).
16
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): PGA308
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