参数资料
型号: PI6C103
厂商: Pericom Semiconductor Corp.
英文描述: Precision Clock Synthesizer
中文描述: 精密时钟合成器
文件页数: 4/12页
文件大小: 568K
代理商: PI6C103
225
PS8315-2 04/08/99
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PI6C103
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously
by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external
PCICLK_Foutput. All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low
state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock
off latency is 2 or 3 CPU clocks.
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only. This in fact may not be the way that the
control is designed.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# , PCI_STOP# are shown in a high state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
Power Management Timing
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
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