参数资料
| 型号： | PI6CU877NFE |
| 厂商： | Pericom |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER DDR2 52VFBGA |
| 产品变化通告： | Product Discontinuation 03/Oct/2011 |
| 标准包装： | 364 |
| 类型： | 时钟缓冲器/驱动器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 存储器，DDR2，SDRAM DIMM |
| 输入： | SSTL-18 |
| 输出： | SSTL-18 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:10 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 270MHz |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-VFBGA |
| 供应商设备封装： | 52-VFBGA（4.5x7） |
| 包装： | 托盘 |
1
PS8689G
01/17/06
Description
PI6CU877 is a PLL clock driver family, consisting of PI6CU877,
and PI6CUA877, developed for Registered DDR2 DIMM
applications with 1.8V operation and differential clock input and
output levels.
The device is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to eleven differential pairs of clock
outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,
FBOUT).
TheclockoutputsarecontrolledbyCLK/CLK,FBOUT,FBOUT,the
LVCMOS inputs (OE, OS) and the Analog Power input (AVDD).
WhenOEisLOWtheoutputsexcept FBOUT,FBOUT,aredisabled
whiletheinternalPLLcontinuestomaintainitslocked-infrequency.
OS is a pin that must be tied to GND or VDD.When OS is high, OE
will function as described above. When OS is LOW, OE has no
effect on Y7/Y7, they are free running. When AVDD is grounded,
the PLL is turned off and bypassed for test purposes.
When CLK/CLK are logic low, the device will enter a low power
mode.An input logic detection circuit will detect the logic low level
and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,
FBOUT, and PLL are OFF.
PI6CUx877 is a high-performance, low skew, and low jitter PLL
clock driver, and it is also able to track Spread Spectrum Clocking
(SSC) for reduced EMI.
Features
PLL clock distribution optimized for DDR2-667/533/400
SDRAM applications.
Distributes one differential clock input pair to eleven differ-
ential clock output pairs.
Differential Inputs (CLK, CLK) and (FBIN, FBIN)
Input OE/OS: LVCMOS
Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
External feedback pins (FBIN, FBIN) are used to
synchronize the outputs to the clock input.
Operates at AVDD = 1.8V for core circuit and internal PLL,
and VDDQ = 1.8V for differential output drivers
Packaging (Pb-free & Green):
– 52-ball VFBGA (NF)
PI6CU877 for DDR2-533/400 applications
PI6CUA877 for DDR2-667/533/400 applications
Pin Configuration
PI6CU877
PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
1
2
3
4
5
6
A
Y1
Y0
Y5
Y6
B
Y1
GND
Y6
C
Y2
GND
NB
GND
Y7
D
Y2
VDDQ
OS
Y7
E
CK
VDDQ
NB
VDDQ
FBIN
F
CK
VDDQ
NB
OE
FBIN
G
AGND
VDDQ
FBOUT
H
AVDD
GND
NB
GND
FBOUT
J
Y3
GND
Y8
k
Y3
Y4
Y9
Y8
08-0298
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI6CU877NFEX | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CU877NFX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA T/R |
| PI6CUA877NFE | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CUA877NFEX | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CUA878NFE | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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