参数资料
| 型号： | PI6CU877NFE |
| 厂商： | Pericom |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER DDR2 52VFBGA |
| 产品变化通告： | Product Discontinuation 03/Oct/2011 |
| 标准包装： | 364 |
| 类型： | 时钟缓冲器/驱动器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 存储器，DDR2，SDRAM DIMM |
| 输入： | SSTL-18 |
| 输出： | SSTL-18 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:10 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 270MHz |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-VFBGA |
| 供应商设备封装： | 52-VFBGA（4.5x7） |
| 包装： | 托盘 |
7
PS8689G
01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)(15)
Parameter
Description
Diagram
AVDD, VDDQ = 1.8 ±0.1V
Units
Min.
Nom.
Max.
ten
OE to and Y/Y
see Fig 11
8
ns
tdis
OE to and Y/Y
see Fig 11
8
tjit(cc+)
Cycle-to-cycle jitter
see Fig 4
0
40
ps
tjit(cc-)
0
-40
t()
Static phase offset (11)
see Fig 5
-50
50
t()dyn
Dynamic phase offset
see Fig 10
-50
50
tsk(o)
Output clock skew
see Fig 6
40
tjit(per)
Period jitter(12)
see Fig 7
-40
40
tjit(hper)
Half period jitter(12) 160 to 270 MHz
see Fig 8
-75
75
Half period jitter(12) 271 to 360 MHz
see Fig 8
-50
50
slr(i)
Input clock slew rate
see Fig 9
1
2.5
4
V/ns
Output enable (OE)
see Fig 9
0.5
slr(o)
Output clock slew rate (14, 16)
see Fig 1, 9
1.5
2.5
3
VOX
Outpu differential-pair cross voltage(13)
see Fig 2
(VDDQ/2)
-0.1
(VDDQ/2)
+0.1
V
The PLL on the PI6CUx877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency deviation
0.00
-0.50
%
PI6CUx877 PLL design should target the values below to minimize the SCC induced skew:
PLL Loop Bandwidth
2.0
MHz
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
13. VOX specified at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
08-0298
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI6CU877NFEX | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CU877NFX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA T/R |
| PI6CUA877NFE | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CUA877NFEX | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| PI6CUA878NFE | 功能描述:锁相环 - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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