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参数资料
| 型号： | PI6LC4831AZBIEX |
| 厂商： | PERICOM SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, QCC56 |
| 封装： | 8 X 8 MM, GREEN, MO-137AE, TQFN-56 |
| 文件页数： | 9/14页 |
| 文件大小： | 891K |
| 代理商： | PI6LC4831AZBIEX |
4
www.pericom.com
P-0.1
03/28/11
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PI6LC4831A
Crystal to Differential HCSL/LVCMOS Frequency Synthesizer
Serial Data Interface I2C
The PI6LC4831A is a slave only I2C device that uses standard I2C protocol. Within any Byte, transmit direction is always from MSB
to LSB.
Read/Write Example:
A read or write to the PI6LC4831A always consists of a Start bit, Address Byte, four Data Bytes, and a stop bit. All values are latched
upon the IC receiving the Stop bit.
How to Write (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
(M) Start
bit
(M) Ad-
dress
(S)Ack
(M) Data
Byte 0
(S)Ack
…
(M) Data
Byte3
(S)Ack
(M) Stop
bit
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
8 bits
1 bit
8 bits
1 bit
…
8 bits
1 bit
(M) Start bit (M) Send
read address (S) Ack
(S) Send
Data Byte 0 (M) Ack
…
(S) Data
Byte3
(M) Not Ac-
knowledge
(M) Stop bit
Note that after the last Data Byte is sent by the slave, there is no Ack pulse. SData remains high.
START:
A Start bit is defined as a HIGH to LOW transition on SDATA while SCLK is high.
DATA:
Data may change only when SCLK is LOW and must be stable when SCLK is HIGH. See Data Byte
descriptions for detail on the functionality of the bit settings.
ACKNOWLEDGE:
SDATA is driven LOW by the PI6LC4831A before the SCLK rising edge and held LOW until the SCLK
falling edge.
STOP:
A Stop bit is defined as a LOW to HIGH transition on SDATA while SCLK is High.
11-0032
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相关代理商/技术参数 |
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| PI6PCIEB24ZDE | 功能描述:时钟缓冲器 1:4 PCI Express Gen2 Zero Delay Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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