参数资料
| 型号： | PI74ALVCH16823A |
| 厂商： | Pericom |
| 文件页数： | 1/7页 |
| 文件大小： | 0K |
| 描述： | IC 18-BIT INTERFACE-F/F 56-TSSOP |
| 产品变化通告： | Product Discontinuation 17/Feb/2006 |
| 标准包装： | 35 |
| 系列： | 74ALVCH |
| 功能： | 主复位 |
| 类型： | D 型总线 |
| 输出类型： | 三态非反相 |
| 元件数： | 2 |
| 每个元件的位元数： | 9 |
| 频率 - 时钟： | 150MHz |
| 触发器类型： | 正边沿 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 2.3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 包装： | 管件 |
1
PS8103A 05/30/06
Logic Block Diagram
Product Description
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed for
2.3V to 3.6V VCC operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-
impedance loads. This device is particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus
drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one
18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the
D-type flip-flops enter data on the low-to-high transitions of the
clock. Taking CLKEN HIGH disables the clock buffer, thus
latching the outputs. Taking the Clear (CLR) input LOW causes the
Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Features
Designed for low voltage operation, VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
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PI74ALVCH16823
18-Bit Bus-Interface Flip-Flop
with 3-State Outputs
06-0148
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI74ALVCH16823V | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18-Bit D-Type Flip-Flop |
| PI74ALVCH16825 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Logic | 18-Bit Buffer/Line Driver |
| PI74ALVCH16825A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:9-Bit Buffer/Driver |
| PI74ALVCH16825V | 制造商:未知厂家 制造商全称:未知厂家 功能描述:9-Bit Buffer/Driver |
| PI74ALVCH16827 | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:20-Bit Buffer/Driver with 3-STATE Outputs |
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