参数资料
型号: PIC12CE673-10E/P
厂商: Microchip Technology
文件页数: 126/129页
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D&EE 8DIP
产品培训模块: Asynchronous Stimulus
标准包装: 60
系列: PIC® 12C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: OTP
EEPROM 大小: 16 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
PIC12C67X
DS30561B-page 96
1999 Microchip Technology Inc.
Output High Voltage
D090
I/O ports (Note 3)
VOH
VDD - 0.7
——
VIOH = -3.0 mA, VDD = 4.5V,
–40
°C to +85°C
D090A
VDD - 0.7
——
VIOH = -2.5 mA, VDD = 4.5V,
–40
°C to +125°C
D092
OSC2/CLKOUT
VDD - 0.7
V
IOH = 1.3 mA, VDD = 4.5V,
–40
°C to +85°C
D092A
VDD - 0.7
V
IOH = 1.0 mA, VDD = 4.5V,
–40
°C to +125°C
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
——
15
pF
In XT and LP modes when
external clock is used to drive
OSC1.
D101
All I/O pins
CIO
——
50
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C
≤ TA ≤ +70°C (commercial)
–40°C
≤ TA ≤ +85°C (industrial)
–40°C
≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ
Max
Units
Conditions
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1:
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
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