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| 型号： | PIC12F510-E/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 3/39页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 1.5KB 8SOIC |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 100 |
| 系列： | PIC® 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 8MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 1.5KB（1K x 12） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 38 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 数据转换器： | A/D 4x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 配用： | AC162070-ND - HEADER INTRFC MPLAB ICD2 8/14P |
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11
6462AS–ATARM–03-Jun-09
AT91SAM9G10
5.
Power Considerations
5.1
Power Supplies
The AT91SAM9G10 has six types of power supply pins:
VDDCORE pins: Power the core, including the processor, the memories and the peripherals;
voltage ranges from 1.08V and 1.32V, 1.2V nominal.
VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to
1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal.
VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
2.7V and 3.6V, 3.3V nominal.
VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.08V and 1.32V, 1.2V nominal.
VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These
supplies enable the user to power the device differently for interfacing with memories and for
interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Sep-
arated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are
GNDBU, GNDOSC and GNDPLL, respectively.
6.
I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied
to VDDBU). It integrates a permanent pull-down resistor of about 15 k
Ω to GNDBU, so that it can
be left unconnected for normal operations.
The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low
level. It integrates a permanent pull-up resistor of about 15 k
Ω to VDDIOP, so that it can be left
unconnected for normal operations.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 k
Ω to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
6.3
Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can
be left unconnected in case no reset from the system needs to be applied to the product.
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