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参数资料
| 型号： | PIC12F675T-I/MD |
| 厂商： | Microchip Technology |
| 文件页数： | 7/35页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 1KX14 8DFN |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 3,300 |
| 系列： | PIC® 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 1.75KB（1K x 14） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 数据转换器： | A/D 4x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 配用： | AC164326-ND - MODULA SKT PM3 20QFN |
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15
0787E–MICRO–3/06
AT89S53
UART
The UART in the AT89S53 operates the same way as the
UART in the AT89C51, AT89C52 and AT89C55. For fur-
ther information, see the October 1995 Microcontroller
Data Book, page 2-49, section titled, “Serial Interface.”
Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the AT89S53 and
peripheral devices or between several AT89S53 devices.
The AT89S53 SPI features include the following:
Full-duplex, 3-wire Synchronous Data Transfer
Master or Slave Operation
1.5 MHz Bit Frequency (max.)
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wakeup from Idle Mode (Slave Mode Only)
The interconnection between master and slave CPUs with
SPI is shown in the following figure. The SCK pin is the
clock output in the master mode but is the clock input in the
slave mode. Writing to the SPI data register of the master
CPU starts the SPI clock generator, and the data written
shifts out of the MOSI pin and into the MOSI pin of the
slave CPU. After shifting one byte, the SPI clock generator
stops, setting the end of transmission flag (SPIF). If both
the SPI interrupt enable bit (SPIE) and the serial port inter-
rupt enable bit (ES) are set, an interrupt is requested.
The Slave Select input, SS/P1.4, is set low to select an
individual SPI device as a slave. When SS/P1.4 is set high,
the SPI port is deactivated and the MOSI/P1.5 pin can be
used as an input.
There are four combinations of SCK phase and polarity
with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are
Figure 7. SPI Master-slave Interconnection
Figure 8. SPI transfer Format with CPHA = 0
*Not defined but normally MSB of character just received
8-BIT SHIFT REGISTER
MASTER
CLOCK GENERATOR
SPI
MISO
8-BIT SHIFT REGISTER
SLAVE
MISO
MOSI MOSI
SCK
SS
V
CC
MSB
LSB
MSB
LSB
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