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参数资料
型号： PIC12F683-I/SN
厂商： Microchip Technology
文件页数： 171/176页
文件大小： 0K
描述： IC MCU FLASH 2KX14 8SOIC
产品培训模块： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 应用说明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装： 100
系列： PIC® 12F
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 5
程序存储器容量： 3.5KB（2K x 14）
程序存储器类型： 闪存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 4x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 8-SOIC（0.154"，3.90mm 宽）
包装： 管件
产品目录页面： 645 (CN2011-ZH PDF)
配用： AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名称： PIC12F683-I/SNG
PIC12F683-I/SNG-ND
PIC12F683
DS41211D-page 92
2007 Microchip Technology Inc.
12.4
Interrupts
The PIC12F683 has multiple interrupt sources:
External Interrupt GP2/INT
Timer0 Overflow Interrupt
GPIO Change Interrupts
Comparator Interrupt
A/D Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
EEPROM Data Write Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
The GIE is cleared to disable any further interrupt.
The return address is pushed onto the stack.
The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
INT Pin Interrupt
GPIO Change Interrupt
Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the PIR1
register. The corresponding interrupt enable bit is
contained in the PIE1 register.
The following interrupt flags are contained in the PIR1
register:
EEPROM Data Write Interrupt
A/D Interrupt
Comparator Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
For external interrupt events, such as the INT pin or
GPIO change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For
additional
information
on
Timer1,
Timer2,
comparators, ADC, data EEPROM or Enhanced CCP
modules, refer to the respective peripheral section.
12.4.1
GP2/INT INTERRUPT
The
external
interrupt
on
the
GP2/INT
pin
is
edge-triggered; either on the rising edge if the INTEDG
bit of the OPTION register is set, or the falling edge, if
the INTEDG bit is clear. When a valid edge appears on
the GP2/INT pin, the INTF bit of the INTCON register is
set. This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The GP2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 12-10 for timing of wake-up from Sleep through
GP2/INT interrupt.
Note 1: Individual interrupt flag bits are set,
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
Note:
The ANSEL and CMCON0 registers must
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0’ and cannot
generate an interrupt.
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