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参数资料
型号： PIC12F683-I/SN
厂商： Microchip Technology
文件页数： 3/176页
文件大小： 0K
描述： IC MCU FLASH 2KX14 8SOIC
产品培训模块： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 应用说明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装： 100
系列： PIC® 12F
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 5
程序存储器容量： 3.5KB（2K x 14）
程序存储器类型： 闪存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 4x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 8-SOIC（0.154"，3.90mm 宽）
包装： 管件
产品目录页面： 645 (CN2011-ZH PDF)
配用： AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名称： PIC12F683-I/SNG
PIC12F683-I/SNG-ND
PIC12F683
DS41211D-page 98
2007 Microchip Technology Inc.
12.7
Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP
instruction.
If the Watchdog Timer is enabled:
WDT will be cleared but keeps running.
PD bit in the STATUS register is cleared.
TO bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before SLEEP
was executed (driving high, low or high-impedance).
For lowest current consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are
high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS for
lowest current consumption. The contribution from
on-chip pull-ups on GPIO should be considered.
The MCLR pin must be at a logic high level.
12.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin.
2.
Watchdog
Timer
wake-up
(if
WDT
was
enabled).
3.
Interrupt from GP2/INT pin, GPIO change or a
peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of a device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
2.
ECCP Capture mode interrupt.
3.
A/D conversion (when A/D clock source is FRC).
4.
EEPROM write operation completion.
5.
Comparator output changes state.
6.
Interrupt-on-change.
7.
External Interrupt from INT pin.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs before the execution of a
SLEEP
instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
Immediately wake-up from Sleep. The SLEEP
instruction is executed. Therefore, the WDT and
WDT prescaler and postscaler (if enabled) will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction. See
Figure 12-10 for more details.
Note:
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
Note:
If the global interrupts are disabled (GIE is
cleared) and any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep.
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