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参数资料
型号： PIC14000-20/SO
厂商： Microchip Technology
文件页数： 96/153页
文件大小： 0K
描述： IC MCU OTP 4KX14 A/D 28SOIC
产品培训模块： Asynchronous Stimulus
标准包装： 27
系列： PIC® 14
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
连通性： I²C
外围设备： POR，温度传感器，WDT
输入/输出数： 20
程序存储器容量： 7KB（4K x 14）
程序存储器类型： OTP
RAM 容量： 192 x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 6 V
数据转换器： 斜率 A/D
振荡器型： 内部
工作温度： 0°C ~ 70°C
封装/外壳： 28-SOIC（0.295"，7.50mm 宽）
包装： 管件
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 47
PIC14000
7.4
Multi-Master Operation
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
7.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 7-11) and turns off its data output stage. A
master which lost arbitrating can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning
master-transmitter may be addressing it.
Arbitration is not allowed between:
A repeated START
A STOP and a data bit
A repeated START and a STOP
Care needs to be taken to ensure that these conditions
do not occur.
7.4.2
CLOCK SYNCHRONIZATION
Clock synchronization occurs after the devices have
started
arbitration.
This
is
performed
using
a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high
transition of this clock may not change the state of the
SCL line, if another device clock is still within its low
period. The SCL line is held low by the device with the
longest low period. Devices with shorter low periods
enter a high wait-state, until the SCL line comes high.
When the SCL line comes high, all devices start
counting off their high periods. The rst device to
complete its high period will pull the SCL line low. The
SCA line high time is determined by the device with the
shortest high period. This is shown in the Figure 7-12.
FIGURE 7-11: MULTI-MASTER
ARBITRATION (2 MASTERS)
FIGURE 7-12: I2C CLOCK
SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1≠ SDA
DATA 1
DATA 2
SDA
SCL
wait
state
start counting
HIGH period
CLK
1
CLK
2
SCL
counter
reset
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PIC14000T-04/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC14000T-04/SS 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC14000T-04I/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC14000T-04I/SS 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC14000T-20/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 20 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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