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参数资料
型号： PIC16CR73-E/SP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP28
封装： 0.300 INCH, PLASTIC, DIP-28
文件页数： 154/172页
文件大小： 2964K
代理商： PIC16CR73-E/SP
PIC16CR7X
DS21993C-page 80
2007 Microchip Technology Inc.
10.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled
by
setting
either
enable
bit
SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
by
setting/clearing
enable
bit
RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG, in
order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3.
Ensure bits CREN and SREN are clear.
4.
If interrupts are desired, then set enable bit
RCIE.
5.
If 9-bit reception is desired, then set bit RX9.
6.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
FIGURE 10-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1 Q2 Q3 Q4
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