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参数资料
型号： PIC16CR73-E/SP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP28
封装： 0.300 INCH, PLASTIC, DIP-28
文件页数： 76/172页
文件大小： 2964K
代理商： PIC16CR73-E/SP
2007 Microchip Technology Inc.
DS21993C-page 165
PIC16CR7X
SSPIF bit ............................................................................. 23
SSPM<3:0> bits .................................................................. 61
SSPOV bit ........................................................................... 61
Stack ................................................................................... 26
Overflows .................................................................... 26
Underflow.................................................................... 26
STATUS Register
DC Bit.......................................................................... 19
IRP Bit......................................................................... 19
PD Bit.......................................................................... 93
TO Bit.................................................................... 19, 93
Z Bit............................................................................. 19
Synchronous Serial Port Enable bit (SSPEN)..................... 61
Synchronous Serial Port Interrupt bit (SSPIF) .................... 23
Synchronous Serial Port Mode Select bits (SSPM<3:0>) ... 61
Synchronous Serial Port. See SSP
T
T1CKPS0 bit ....................................................................... 47
T1CKPS1 bit ....................................................................... 47
T1OSCEN bit ...................................................................... 47
T1SYNC bit ......................................................................... 47
T2CKPS0 bit ....................................................................... 52
T2CKPS1 bit ....................................................................... 52
TAD
....................................................................................... 87
Time-out Sequence............................................................. 94
Timer0 ................................................................................. 43
Associated Registers .................................................. 45
Clock Source Edge Select (T0SE Bit)......................... 20
Clock Source Select (T0CS Bit).................................. 20
External Clock............................................................. 44
Interrupt....................................................................... 43
Overflow Enable (TMR0IE Bit).................................... 21
Overflow Flag (TMR0IF Bit) ...................................... 100
Overflow Interrupt ..................................................... 100
Prescaler..................................................................... 45
RA4/T0CKI Pin, External Clock .............................. 8, 10
T0CKI.......................................................................... 44
Timer1 ................................................................................. 47
Associated Registers .................................................. 50
Asynchronous Counter Mode ..................................... 49
Capacitor Selection ..................................................... 50
Counter Operation ...................................................... 48
Operation in Timer Mode ............................................ 48
Oscillator ..................................................................... 50
Prescaler..................................................................... 50
RC0/T1OSO/T1CKI Pin .......................................... 9, 11
RC1/T1OSI/CCP2 Pin............................................. 9, 11
Resetting of Timer1 Registers .................................... 50
Resetting Timer1 using a CCP Trigger Output ........... 50
Synchronized Counter Mode ...................................... 48
TMR1H Register ......................................................... 49
TMR1L Register.......................................................... 49
Timer2 ................................................................................. 51
Associated Registers .................................................. 52
Output ......................................................................... 51
Postscaler ................................................................... 51
Prescaler..................................................................... 51
Prescaler and Postscaler ............................................ 51
Timing Diagrams
A/D Conversion ......................................................... 137
Brown-out Reset ....................................................... 126
Capture/Compare/PWM (CCP1 and CCP2) ............. 128
CLKOUT and I/O....................................................... 125
External Clock........................................................... 124
I2C Bus Data ............................................................. 133
I2C Bus Start/Stop Bits ............................................. 132
I2C Reception (7-bit Address)..................................... 67
I2C Transmission (7-bit Address) ............................... 67
Parallel Slave Port .................................................... 129
Parallel Slave Port Read Waveforms ......................... 41
Parallel Slave Port Write Waveforms ......................... 41
Power-up Timer ........................................................ 126
PWM Output ............................................................... 57
RESET...................................................................... 126
Slow Rise Time (MCLR Tied to VDD
Through RC Network)......................................... 98
SPI Master Mode (CKE = 0, SMP = 0) ..................... 130
SPI Master Mode (CKE = 1, SMP = 1) ..................... 130
SPI Mode (Master Mode) ........................................... 63
SPI Mode (Slave Mode with CKE = 0)........................ 63
SPI Mode (Slave Mode with CKE = 1)........................ 64
SPI Slave Mode (CKE = 0) ....................................... 131
SPI Slave Mode (CKE = 1) ....................................... 131
Start-up Timer........................................................... 126
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ................................................................ 98
Case 2 ................................................................ 98
Time-out Sequence on Power-up
(MCLR Tied to VDD Through RC Network)......... 97
Timer0 ...................................................................... 127
Timer1 ...................................................................... 127
USART Asynchronous Master Transmission ............. 74
USART Asynchronous Master Transmission
(Back to Back) ................................................... 75
USART Asynchronous Reception .............................. 76
USART Synchronous Receive (Master/Slave) ......... 135
USART Synchronous Reception
(Master Mode, SREN) ........................................ 80
USART Synchronous Transmission ........................... 79
USART Synchronous Transmission
(Master/Slave) .................................................. 135
USART Synchronous Transmission
(Through TXEN) ................................................. 79
Wake-up from Sleep via Interrupt............................. 103
Watchdog Timer ....................................................... 126
Timing Parameter Symbology .......................................... 123
Timing Requirements
Capture/Compare/PWM (CCP1 and CCP2)............. 128
CLKOUT and I/O ...................................................... 125
External Clock .......................................................... 124
I2C Bus Data............................................................. 134
I2C Bus Start/Stop Bits............................................. 133
Parallel Slave Port .................................................... 129
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out Reset . 126
SPI Mode .................................................................. 132
Timer0 and Timer1 External Clock ........................... 127
USART Synchronous Receive ................................. 135
USART Synchronous Transmission ......................... 135
TMR1CS bit ........................................................................ 47
TMR1ON bit........................................................................ 47
TMR2ON bit........................................................................ 52
TOUTPS<3:0> bits ............................................................. 52
TRISA Register................................................................... 31
TRISB Register................................................................... 33
TRISC Register................................................................... 35
TRISD Register................................................................... 36
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