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参数资料
型号： PIC16CR77T-I/ML
厂商： Microchip Technology
文件页数： 86/172页
文件大小： 0K
描述： IC PIC MCU 8KX14 44QFN
标准包装： 1,600
系列： PIC® 16C
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 33
程序存储器容量： 14KB（8K x 14）
程序存储器类型： ROM
RAM 容量： 368 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 8x8b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-VQFN 裸露焊盘
包装： 带卷 (TR)
PIC16CR7X
DS21993C-page 18
2007 Microchip Technology Inc.
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
101h
TMR0
Timer0 Module Register
xxxx xxxx
45, 96
102h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
103h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
19, 96
104h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
105h
—
Unimplemented
—
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
34, 96
107h
—
Unimplemented
—
108h
—
Unimplemented
—
109h
—
Unimplemented
—
10Ah(1,4) PCLATH
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
10Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
10Ch
PMDATA
Data Register Low Byte
xxxx xxxx
29, 97
10Dh
PMADR
Address Register Low Byte
xxxx xxxx
29, 97
10Eh
PMDATH
—
Data Register High Byte
xxxx xxxx
29, 97
10Fh
PMADRH
—
Address Register High Byte
xxxx xxxx
29, 97
Bank 3
180h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
20, 44, 96
182h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
183h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
19, 96
184h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
185h
—
Unimplemented
—
186h
TRISB
PORTB Data Direction Register
1111 1111
34, 96
187h
—
Unimplemented
—
188h
—
Unimplemented
—
189h
—
Unimplemented
—
18Ah(1,4) PCLATH
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
18Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
18Ch
PMCON1
— (6)
—
—RD
1--- ---0
29, 97
18Dh
—
Unimplemented
—
18Eh
—
Reserved maintain clear
0000 0000
18Fh
—
Reserved maintain clear
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page
Legend:
x
= unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2:
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6:
This bit always reads as a ‘1’.
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