参数资料
型号: PIC16F1826-I/ML
厂商: Microchip Technology
文件页数: 30/109页
文件大小: 0K
描述: IC PIC MCU FLASH 2K 28-QFN
产品培训模块: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
特色产品: Extreme Low Power (XLP) Microcontrollers
标准包装: 61
系列: PIC® XLP™ mTouch™ 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 32MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 12x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-VQFN 裸露焊盘
包装: 托盘
产品目录页面: 655 (CN2011-ZH PDF)
185
2570N–AVR–05/11
ATmega325/3250/645/6450
21. USI – Universal Serial Interface
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load. The main features of the USI are:
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wake up from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
21.1
Overview
A simplified block diagram of the USI is shown on Figure 21-1. For the actual placement of I/O
CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-
specific I/O Register and bit locations are listed in the “Register Descriptions” on page 192.
Figure 21-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock
source. This allows the counter to count the number of bits received or transmitted and generate
DATA
BUS
USIPF
USITC
USICLK
USICS0
USICS1
USIOIF
USIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE
Bit7
Two-wire Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
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