参数资料
型号: PIC16F526-E/P
厂商: Microchip Technology
文件页数: 102/122页
文件大小: 0K
描述: IC PIC MCU FLASH 1KX12 14DIP
产品培训模块: 8-bit PIC® Microcontroller Portfolio
标准包装: 30
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: POR,WDT
输入/输出数: 11
程序存储器容量: 1.5KB(1K x 12)
程序存储器类型: 闪存
RAM 容量: 67 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 3x8b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 14-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 638 (CN2011-ZH PDF)
配用: AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 80
2009 Microchip Technology Inc.
FIGURE 7-2:
TABLE WRITE OPERATION
7.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data
EEPROM
memory.
When
set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
selection access is determined by EEPGD.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Table Pointer(1)
Table Latch (8-bit)
TBLPTRH
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Holding Registers
Program Memory
Note:
During normal operation, the WRERR bit
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
Note:
The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
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