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参数资料
| 型号： | PIC16F74T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 102/104页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 4KX14 A/D 44TQFP |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 1,200 |
| 系列： | PIC® 16F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 33 |
| 程序存储器容量： | 7KB（4K x 14） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 192 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 数据转换器： | A/D 8x8b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-TQFP |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
KSZ8851-16MLLJ
March 2010
89
M9999-030210-1.0
Acronyms and Glossary
BIU
Bus Interface Unit
The host interface function that performs code conversion, buffering,
and the like required for communications to and from a network.
BPDU
Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
CMOS
Complementary Metal Oxide Semiconductor
A common semiconductor manufacturing technique in which positive
and negative types of transistors are combined to form a current gate
that in turn forms an effective means of controlling electrical current
through a chip.
CRC
Cyclic Redundancy Check
A common technique for detecting data transmission errors. CRC for
Ethernet is 32 bits long.
Cut-through switch
A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it
needs to go, then forwarding it. A cut-through switch simply reads in
the first bit of an incoming packet and forwards the packet. Cut-
through switches do not store the packet.
DA
Destination Address
The address to send packets.
DMA
Direct Memory Access
A design in which memory on a chip is controlled independently of
the CPU.
EEPROM
Electronically Erasable Programmable Read-only Memory
A design in which memory on a chip can be erased by exposing it to
an electrical charge.
EISA
Extended Industry Standard Architecture
A bus architecture designed for PCs using 80x86 processors, or an
Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32
bits wide and support multiprocessing.
EMI
Electro-Magnetic Interference
A naturally occurring phenomena when the electromagnetic field of
one device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer
technology, computer devices are susceptible to EMI because
electromagnetic fields are a byproduct of passing electricity through a
wire. Data lines that have not been properly shielded are susceptible
to data corruption by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IGMP
Internet Group Management Protocol
The protocol defined by RFC 1112 for IP multicast transmissions.
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium has
to be "silent" (i.e., no data transfer) for a short period of time before a
node can consider the network idle and start to transmit. IPG is used
to correct timing differences between a transmitter and receiver.
During the IPG, no data is transferred, and information in the gap can
be discarded or additions inserted without impact on data integrity.
ISI
Inter-Symbol Interference
The disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA
Industry Standard Architecture
A bus architecture used in the IBM PC/XT and PC/AT.
Jumbo Packet
A packet larger than the standard Ethernet packet (1500 bytes).
Large packet sizes allow for more efficient use of bandwidth, lower
overhead, less processing, etc.
MDI
Medium Dependent Interface
An Ethernet port connection that allows network hubs or switches to
connect to other hubs or switches without a null-modem, or
crossover, cable. MDI provides the standard interface to a particular
media (copper or fiber) and is therefore 'media dependent.'
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