参数资料
型号: PIC16LF1527T-I/MR
厂商: Microchip Technology
文件页数: 37/94页
文件大小: 0K
描述: MCU PIC 28KB FLASH 64QFN
标准包装: 3,300
系列: PIC® XLP™ 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 54
程序存储器容量: 28KB(16K x 14)
程序存储器类型: 闪存
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 30x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
203
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
20.8
Register Description
The following section describes the registers used for SPI operation using the USART.
20.8.1
UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
20.8.2
UCSRnA – USART MSPIM Control and Status Register n A
Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
20.8.3
UCSRnB – USART MSPIM Control and Status Register n B
Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
Bit
7
6
5
4
3
2
1
0
RXCn
TXCn
UDREn
-
UCSRnA
Read/Write
R
R/W
R
Initial Value
0
1
0
Bit
7
65
43
2
1
0
RXCIEn
TXCIEn
UDRIE
RXENn
TXENn
-
UCSRnB
Read/Write
R/W
R
Initial Value
0
1
0
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