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参数资料
| 型号： | PIC16LF1824-E/P |
| 厂商： | Microchip Technology |
| 文件页数： | 23/101页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 7KB FLASH 14PDIP |
| 标准包装： | 30 |
| 系列： | PIC® XLP™ mTouch™ 16F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 32MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 11 |
| 程序存储器容量： | 7KB（4K x 14） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
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169
2552K–AVR–04/11
ATmega329/3290/649/6490
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
19.2.1
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
Bit locations inside all USART Registers.
Baud Rate Generation.
Transmitter Operation.
Transmit Buffer Functionality.
Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
A second Buffer Register has been added. The two Buffer Registers operate as a circular
FIFO buffer. Therefore the UDRn must only be read once for each incoming data! More
important is the fact that the Error Flags (FEn and DORn) and the ninth data bit (RXB8n) are
buffered with the data in the receive buffer. Therefore the status bits must always be read
before the UDRn Register is read. Otherwise the error status will be lost since the buffer
state is lost.
The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
received data to remain in the serial Shift Register (see Figure 19-1) if the Buffer Registers
are full, until a new start bit is detected. The USART is therefore more resistant to Data
OverRun (DORn) error conditions.
The following control bits have changed name, but have same functionality and register location:
CHR9 is changed to UCSZn2.
OR is changed to DORn.
19.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCK pin is only active when using synchronous mode.
Figure 19-2 shows a block diagram of the clock generation logic.
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| PIC16LF1824-I/ML | 功能描述:8位微控制器 -MCU 7KB Flash 256B RAM 32 MHz Int Osc Core RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LF1824-I/P | 功能描述:8位微控制器 -MCU 7KB Flash 256B RAM 32 MHz Int Osc Core RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LF1824-I/SL | 功能描述:8位微控制器 -MCU 7KB Flash 256B RAM 32 MHz Int Osc Core RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LF1824-I/ST | 功能描述:8位微控制器 -MCU 7KB Flash 256B RAM 32 MHz Int Osc Core RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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