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参数资料
型号： PIC16LF1947T-I/MR
厂商： Microchip Technology
文件页数： 10/46页
文件大小： 0K
描述： MCU 8BIT 28KB FLASH 64QFN
标准包装： 3,300
系列： PIC® XLP™ 16F
核心处理器： PIC
芯体尺寸： 8-位
速度： 32MHz
连通性： I²C，LIN，SPI，UART/USART
外围设备： 欠压检测/复位，LCD，POR，PWM，WDT
输入/输出数： 54
程序存储器容量： 28KB（16K x 14）
程序存储器类型： 闪存
EEPROM 大小： 256 x 8
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
数据转换器： A/D 17x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-VFQFN 裸露焊盘
包装： 带卷 (TR)
配用： MA160016-ND - MODULE PLUG-IN PIC16F1947
MA160015-ND - MODULE PLUG-IN PIC16LF1947
DM240313-ND - BOARD DEMO 8BIT XLP
PIC16F193X/LF193X/PIC16F194X/LF194X/
DS41397B-page 18
2010 Microchip Technology Inc.
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration
memory
can
be
accessed
and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering
Program/Verify
mode,
all
I/O’s
are
automatically configured as high-impedance inputs
and the address is cleared.
4.1
High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
VPP – First entry mode
VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1.
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
2.
Raise the voltage on MCLR from 0V to VIHH.
3.
Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and RB6 and RB7 are driven by the user
application, the device will execute code. Since this
may prevent entry, VPP-first entry mode is strongly
recommended. See the timing diagram in Figure 8-3.
4.1.2
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1.
Hold ICSPCLK and ICSPDAT low.
2.
Raise the voltage on VDD from 0V to the desired
operating voltage.
3.
Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-2.
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-4 and 8-5.
4.2
Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16F193X/LF193X/PIC16F194X/LF194X/
PIC16LF190X devices to be programmed using VDD
only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to ‘1’, the low-
voltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
MCLR is brought to VIL.
2.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figures 8-9
and 8-10.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figures 8-9 and 8-10.
Note:
To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
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