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参数资料
型号： PIC17C766T-33I/PT
厂商： Microchip Technology
文件页数： 88/159页
文件大小： 0K
描述： IC MCU OTP 16KX16 A/D 80TQFP
标准包装： 1,200
系列： PIC® 17C
核心处理器： PIC
芯体尺寸： 8-位
速度： 33MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 66
程序存储器容量： 32KB（16K x 16）
程序存储器类型： OTP
RAM 容量： 902 x 8
电压 - 电源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
数据转换器： A/D 16x10b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 80-TQFP
包装： 带卷 (TR)
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
2000 Microchip Technology Inc.
DS30289B-page 33
PIC17C7XX
6.0
INTERRUPTS
PIC17C7XX devices have 18 sources of interrupt:
External interrupt from the RA0/INT pin
Change on RB7:RB0 pins
TMR0 Overflow
TMR1 Overflow
TMR2 Overflow
TMR3 Overflow
USART1 Transmit buffer empty
USART1 Receive buffer full
USART2 Transmit buffer empty
USART2 Receive buffer full
SSP Interrupt
SSP I2C bus collision interrupt
A/D conversion complete
Capture1
Capture2
Capture3
Capture4
T0CKI edge occurred
There are six registers used in the control and status of
interrupts. These are:
CPUSTA
INTSTA
PIE1
PIR1
PIE2
PIR2
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Section 6.4.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupts, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts, which
all vector to the same address). These sources are:
External interrupt from the RA0/INT pin
TMR0 Overflow
T0CKI edge occurred
Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupts), the interrupt flag bit is automatically cleared.
Vectoring to the peripheral interrupt vector address
does not automatically clear the source of the interrupt.
In the peripheral Interrupt Service Routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
When an interrupt condition is met, that individual inter-
rupt flag bit will be set, regardless of the status of its
corresponding mask bit or the GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two-cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the Interrupt Service Routine.
When this instruction is executed, the stack is “POPed”
and the GLINTD bit is cleared (to re-enable interrupts).
FIGURE 6-1:
INTERRUPT LOGIC
RBIF
RBIE
TMR3IF
TMR3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA2IF
CA2IE
CA1IF
CA1IE
TX1IF
TX1IE
RC1IF
RC1IE
T0IF
T0IE
INTF
INTE
T0CKIF
T0CKIE
GLINTD (CPUSTA<4>)
PEIE
Wake-up (If in SLEEP mode)
or terminate long write
Interrupt to CPU
PEIF
SSPIF
SSPIE
BCLIF
BCLIE
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
P
IR1
/PIE
1
P
IR2/P
IE
2
INTSTA
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