参数资料
型号: PIC18F458T-I/PT
厂商: Microchip Technology
文件页数: 88/116页
文件大小: 0K
描述: IC MCU FLASH 16KX16 W/CAN 44TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 带卷 (TR)
2006 Microchip Technology Inc.
DS41159E-page 71
PIC18FXX8
6.5
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
Read 64 bytes into RAM.
2.
Update data values in RAM as necessary.
3.
Load Table Pointer with address being erased.
4.
Do the row erase procedure.
5.
Load Table Pointer with address of first byte
being written.
6.
Write the first 8 bytes into the holding registers
using the TBLWT instruction, auto-increment
may be used.
7.
Set the EECON1 register for the write operation:
set the EEPGD bit to point to program memory;
clear the CFGS bit to access program memory;
set the WREN to enable byte writes.
8.
Disable interrupts.
9.
Write 55h to EECON2.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6-14 seven times to write
64 bytes.
15. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 8 bytes in
the holding registers.
Holding Register
TABLAT
Holding Register
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxxx0
8
Write Register
TBLPTR = xxxxx2
Program Memory
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