参数资料
型号: PIC18F6520-I/PT
厂商: Microchip Technology
文件页数: 157/165页
文件大小: 0K
描述: IC MCU FLASH 16KX16 EEPROM64TQFP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 160
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 52
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 12x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
产品目录页面: 643 (CN2011-ZH PDF)
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
2004 Microchip Technology Inc.
DS39609B-page 89
PIC18F6520/8520/6620/8620/6720/8720
9.1
INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON REGISTER
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1
= Enables all unmasked interrupts
0
= Disables all interrupts
When IPEN (RCON<7>) = 1:
1
= Enables all high priority interrupts
0
= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1
= Enables all low priority peripheral interrupts
0
= Disables all low priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 overflow interrupt
0
= Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1
= Enables the INT0 external interrupt
0
= Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1
= The INT0 external interrupt occurred (must be cleared in software)
0
= The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1
= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0
= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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