参数资料
型号: PIC18F6520-I/PT
厂商: Microchip Technology
文件页数: 29/165页
文件大小: 0K
描述: IC MCU FLASH 16KX16 EEPROM64TQFP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 160
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 52
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 12x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
产品目录页面: 643 (CN2011-ZH PDF)
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 122
2004 Microchip Technology Inc.
10.8
PORTH, LATH and TRISH
Registers
PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high-order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
EXAMPLE 10-8:
INITIALIZING PORTH
FIGURE 10-17:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
FIGURE 10-18:
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
Note:
PORTH is available only on PIC18F8X20
devices.
Note 1: On
Power-on
Reset,
PORTH
pins
RH7:RH4 default to A/D inputs and read
as ‘0’.
2: On
Power-on
Reset,
PORTH
pins
RH3:RH0 default to system bus signals.
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
CLRF
LATH
; Alternate method
; to clear output
; data latches
MOVLW
0Fh
;
MOVWF
ADCON1
;
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
Data
Bus
WR LATH
WR TRISH
RD PORTH
Data Latch
TRIS Latch
RD TRISH
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATH
or
PORTH
Note 1: I/O pins have diode protection to VDD and VSS.
Data
Bus
WR LATH
WR TRISH
RD PORTH
Data Latch
TRIS Latch
RD TRISH
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATH
or
PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
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