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参数资料
| 型号： | PIC18F65J90T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 10/41页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 16KX16 64TQFP |
| 产品培训模块： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 标准包装： | 1,200 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LCD，LVD，POR，PWM，WDT |
| 输入/输出数： | 51 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 12x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-TQFP |
| 包装： | 带卷 (TR) |
| 配用： | AC162079-ND - HEADER MPLAB ICD2 18F85J90 64/80 AC164327-ND - MODULE SKT FOR 64TQFP |
| 其它名称： | PIC18F65J90T-I/PTTR |
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LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
18 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.12 SPI serial I/O controller
The SPI is a full duplex serial interface, designed to be able to handle multiple masters
and slaves connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data transfer the
master always sends a byte of data to the slave, and the slave always sends a byte of data
to the master.
6.12.1 Features
Compliant with Serial Peripheral Interface (SPI) specication.
Synchronous, serial, full duplex communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.12.2 Features available in LPC2104/2105/2106/01 only
Selectable transfer width of eight to 16 bit per frame.
When the SPI interface is used in Master mode, the SSEL pin is not needed (can be
used for a different function).
6.13 SSP controller (LPC2104/2015/2106/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data owing from the master to the
slave and from the slave to the master.
Because the SSP and SPI peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
y from SPI to SSP and back.
6.13.1 Features
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
6.14 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specied timer values, based on four
match registers. It also includes up to four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt.
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| PIC18F65K22-E/MR | 功能描述:8位微控制器 -MCU 32KB Flash 2KB RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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