- 您现在的位置：买卖IC网 > PDF目录11496 > PIC18F65J90T-I/PT (Microchip Technology)IC PIC MCU FLASH 16KX16 64TQFP PDF资料下载
参数资料
| 型号： | PIC18F65J90T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 15/41页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 16KX16 64TQFP |
| 产品培训模块： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 标准包装： | 1,200 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LCD，LVD，POR，PWM，WDT |
| 输入/输出数： | 51 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 12x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-TQFP |
| 包装： | 带卷 (TR) |
| 配用： | AC162079-ND - HEADER MPLAB ICD2 18F85J90 64/80 AC164327-ND - MODULE SKT FOR 64TQFP |
| 其它名称： | PIC18F65J90T-I/PTTR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
22 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip Reset and may be enabled by software. The program must congure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100
s.
6.18.3 Reset and wake-up timer
Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch lter. Assertion of
chip Reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a xed number of clocks have passed, and the on-chip ash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufcient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of
security in the system so that access to the on-chip ash and use of the JTAG and ISP
can be restricted. When needed, CRP is invoked by programming a specic pattern into a
dedicated ash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection:
1. CRP1 disables access to the chip via the JTAG and allows partial ash update
(excluding ash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and ash eld updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the JTAG and only allows full ash erase and
update using a reduced set of the ISP commands.
相关PDF资料 |
PDF描述 |
|---|---|
| PIC16C771-I/SO | IC MCU OTP 4KX14 A/D PWM 20SOIC |
| PIC16LC716T-04I/SO | IC MCU OTP 2KX14 A/D PWM 18SOIC |
| PIC16LC711T-04/SO | IC MCU OTP 1KX14 A/D 18SOIC |
| PIC16CE624-04E/P | IC MCU OTP 1KX14 EE COMP 18DIP |
| PIC18F4221T-I/PT | IC PIC MCU FLASH 2KX16 44TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC18F65J94-I/MR | 制造商:Microchip Technology Inc 功能描述:64 PINS, 32KB FLASH, 4KB RAM, 16MIPS, NANOWATT XLP, LCD, USB - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 32KB FLASH 64QFN 制造商:Microchip Technology Inc 功能描述:64 pins, 32KB Flash, 4KB RAM, 16MIPS, nanoWatt XLP, LCD, USB, 64 QFN 9x9x0.9mm T |
| PIC18F65J94-I/PT | 制造商:Microchip Technology Inc 功能描述:64 PINS, 32KB FLASH, 4KB RAM, 16MIPS, NANOWATT XLP, LCD, USB - Trays 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 32KB FLASH 64TQFP |
| PIC18F65J94T-I/MR | 制造商:Microchip Technology Inc 功能描述:MCU 8-bit PIC18 PIC RISC 32KB Flash 2.5V/3.3V 64-Pin QFN EP T/R 制造商:Microchip Technology Inc 功能描述:64 PINS, 32KB FLASH, 4KB RAM, 16MIPS, NANOWATT XLP, LCD, USB - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 32KB FLASH 64QFN 制造商:Microchip Technology Inc 功能描述:8-bit Microcontrollers - MCU 64 pins 32KB Flash 4KB RAM 16MIPS |
| PIC18F65J94T-I/PT | 制造商:Microchip Technology Inc 功能描述:64 PINS, 32KB FLASH, 4KB RAM, 16MIPS, NANOWATT XLP,LCD, USB - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 32KB FLASH 64TQFP 制造商:Microchip Technology Inc 功能描述:8-bit Microcontrollers - MCU 64 pins, 32KB Flash, 4KB RAM, 16MIPS |
| PIC18F65K22-E/MR | 功能描述:8位微控制器 -MCU 32KB Flash 2KB RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。