参数资料
型号: PIC18F66J93-I/PT
厂商: Microchip Technology
文件页数: 30/54页
文件大小: 0K
描述: IC PIC MCU FLASH 64KX4 64-TQFP
产品培训模块: PIC18 J Series MCU Overview
标准包装: 160
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,LCD,LVD,POR,PWM,WDT
输入/输出数: 51
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3923 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 12x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
PIC18F87J93 FAMILY
DS39948A-page 34
Preliminary
2009 Microchip Technology Inc.
2.5
A/D Conversions
Figure 2-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 2-4 shows the operation of the A/D converter
after the GO/DONE bit has been set; the ACQT<2:0>
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
2.6
Use of the CCP2 Trigger
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
FIGURE 2-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
1
2
3
4
5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
TACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
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