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参数资料
型号： PIC18F67K90T-I/PTRSL
厂商： Microchip Technology
文件页数： 25/110页
文件大小： 0K
描述： MCU 8BIT 128K FLASH 64-TQFP
标准包装： 1,200
系列： PIC® XLP™ 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 64MHz
连通性： I²C，LIN，SPI，UART/USART
外围设备： 欠压检测/复位，LCD，POR，PWM，WDT
输入/输出数： 53
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
数据转换器： A/D 16x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-TQFP
包装： 带卷 (TR)
PIC18F47J53 FAMILY
DS39964B-page 472
Preliminary
2010 Microchip Technology Inc.
BTFSC
Bit Test File, Skip if Clear
Syntax:
BTFSC f, b {,a}
Operands:
0
f 255
0
b 7
a
[0,1]
Operation:
skip if (f<b>) = 0
Status Affected:
None
Encoding:
1011
bbba
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (TRUE)
If FLAG<1>
=
1;
PC
=
address (FALSE)
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSS f, b {,a}
Operands:
0
f 255
0
b < 7
a
[0,1]
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
1010
bbba
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSS
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (FALSE)
If FLAG<1>
=
1;
PC
=
address (TRUE)
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PIC18F8310T-I/PT 功能描述:8位微控制器 -MCU 8kBF 768RM 70I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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